Show that the dual of the exclusive-or is equal to its compliment. 7

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1 Darshan Institute of ngineering and Technology, Rajkot, Subject: Digital lectronics (2300) GTU Question ank Unit Group Questions Do as directed : I. Given that (6)0 = (00)x, find the value of x. II. dd (6) 6 and (5) 6 III. (33) 5 = ( ) 0 = ( ) 2 3 Summer-6 Winter-5 Summer-5 Winter- Summer- Winter-3 Summer-3 What are the different types of the codes used in digital systems? xplain them. Do as directed : I. (00000) 2 = ( ) 6 II. Subtract (5) 8 from (66) 8 III. overt the Gray code 0 to binary IV. Find the XS-3 code of 3 Design bit binary to gray code converter. onvert decimal number (0.252)0 to binary with an error less than %. 3 onvert (5) 0 = ( )2 onvert (00) 2 = ( ) 0 onvert (000) 2 = ( ) 6 = ( ) 8 2 What is self-complementing code? Represent (2) 0 in 22 self-complementing code. 2 onvert (96) 0 to its equivalent gray code and X-3 code. Perform addition in D format (9) D + (6) D 3 Perform subtraction of (8) 0 (58) 0 using 2 s complement method. 3 onvert the decimal number 8 to 8-bit binary. onvert the binary number What is the 2 s complement of number 00? Design a D to excess 3 code converter using minimum number of NND gates. overt following: () (.2) 6 = (?) 8 (2) (52.3) 8 = (?) 2 6 Write a brief not on Gray codes. lso discuss methods for conversion from gray to binary code and vice versa onvert the following numbers as directed: () (30) 0 = ( ) 2 (2) (00) 2 = ( ) 0 (3) (00) 2 = ( ) 8 () (0000) 2 =( ) 6 onvert the decimal number to base 3, base, base and base 6. Perform the subtraction with the following decimal numbers using s compliment and 2 s compliments. (a) 00-0, (b) Find the logic required at R input. Show that the dual of the exclusive-or is equal to its compliment. Give following Definitions: () Fan in (2) Fan out (3) Noise margin () Propagation delay Define the followings. ()Fan in (2) Noise margin (3) Propagation delay () Negative logic D Discuss NND gate as universal gate (implement NOT, ND, OR & NOR gate using NND gate). F When used with an I, what does the term QUD indicate?

2 Reduce the expression F = Ʃm(0,2,3,,5,6) using K-map and implement using NND gates only. Using D as the MV, reduce Y = '''D' + ''D' + ''D' + ''D + 'D + 'D'. Minimize following oolean function using K-map & design the simplified function using logic gates. F = Σ m(, 2,, 6,,, 5) + Σ d(0, 3) Reduce the given function using K-map and implement the same using gates. F(,,,D ) = Σm (0,,3,,,5) + Σd ( 2,) Minimize the following logic function using K-maps and realize using NND and NOR gates. F(,,,D) =Σ_m(,3,5,8,9,,5) + d(2,3). Minimise the logic function F (,,,D) = Π_ M (, 2, 3, 8, 9, 0,,) d (, 5) Use Karnaugh map. Draw the logic circuit for the simplified function using NOR gates only. Using K-map find the oolean function and its complement for the following: F(,,,D) = Σ(,2,3,,6,8,9,0,,2,) Simplify the oolean Function with Karnaugh map: F(w,x,y,z) = Ʃ(0,,2,,5,6,8,9,2,3,) and F = ˊˊˊ+ˊDˊ+ˊDˊ+ˊˊ Simplify the oolean Function: F(w,x,y,z) = Ʃ(,3,,,5) and the Don t care conditions : d(w,x,y,z) = Ʃ(0,2,5) 2 Obtain the simplified expression in sum of product for the following oolean functions. (a) F= Σ(0,,,5,0,,2,) and (b) F=Σ (, 2, 3,, 5). Implement the functions F=Σ(,3,,,5) with don t care conditions d=σ(0, 2,5) Discuss the effect of don t care conditions. State and prove De Morgan s Theorems with the help of truth tables. onvert F (,, ) = + into standard minterm form. 3 ttempt following: () overt into Sum-of-Minterms : + + (2) overt into Product-of- Maxtems : ( +)( ) Define the following terms: () Literal (2) Minterm (3) Maxterm 3 Simplify the following oolean functions to a minimum numbers of literals. (a) xyz+x y+xyz and (b)(+) ( + ) combinational circuit has 3 inputs,, and output F. F is true for following input combinations: is False, is True is False, is True,, are False,, are True D (i) Write the Truth table for F. Use the convention True= and False = 0. (ii) Write the simplified expression for F in SOP form. (iii) Write the simplified expression for F in POS form. Reduce the expression F = (() + +) 3 Show that XNOR = + = ( XOR ) = ( + ). lso construct the corresponding logic diagrams. Minimize the following oolean expressions.. X = ( (''')' + (')' )' 2. Y = + ' + ' + '' Simplify using oolean laws and draw the logic diagram for the given expression. Prove the following oolean identities. Simplify : () + + D + D (2) (P+Q+R) (P + Q + R ) P 8 Prove that: () (( +) + (+ )) = 0 (2) + + = + Derive oolean function using Tabulation Method for the following: F(P,Q,R,S) = Σ(0,,3,,5,,0,3,,5) F Simplify the oolean Function by using the tabulation method: F = Ʃ(0,,2,8,0,,,5) Reduce following oolean function and then realize the reduced one using NOR gate only. X = ('+') (+D) G () Draw the logic circuit for following function using only NND gates: F= +ˊ+ˊDˊ (2) Draw the logic circuit for following function using only NOR gates: F= ˊ+( +D) Implement the oolean functions. (a) xyz+x y+xyz (b) (+) ( + ) and (c) F= xy+xy +y z with logic gates. H Obtain the truth table of the function F= xy+xy +y z. I Define Negative logic J Write short note on half adder and full adder.

3 3 What is encoder? With logic circuit and truth table explain the working of Octal to binary ncoder. Give the applications of Decoder. 3 Design a full adder using 3X8 decoder followed by gates. Design X 6 decoder using two 3 X 8 decoder. Design a -to-6 decoder by using only 2- decoder circuits With logic circuit and truth table explain the working of 3 to 8 line decoder. Implement the given function using multiplexer F(,,) = Ʃm(,2,,) xplain the working of multiplexer. 3 Implement following logic function using 8X MUX. F = Σ m(0,, 3, 5,,, 3,, 5) Implement the given function using 8 X Multiplexer F (,,,D) = Σm (0,,2,3,5,8,9,,) Design a 8 to multiplexer by using the four variable function given by F(,,,D) =Σm(0,,3,,8,9,5). What is Multiplexer? With logic circuit and function table explain the working of to line multiplexer. With logic circuit describe the function of: () Full adder (2) Full subtractor. lso write the D simplified oolean functions for their outputs. xplain half and full adders in detail. Draw & explain in brief pin diagram of 85 four-bit magnitude comparator. 3 Design a circuit for 2-bit magnitude comparator. With logic circuit explain the working of -bit magnitude comparator. F Write a brief note on parity checker/generator. Draw & explain in brief a high assertion input SR latch. 3 For the figures, 2, & 3, plot the output waveforms referenced to the clock signal assuming the initial contents of all FFs is Q = 0. ssume all FFs are edge triggered.

4 () Fill in values for S & R to cause the Q values of the SR FF given in figure. (2) 2. Plot the output waveform for the inputs shown in figure 5, assuming the initial contents of the FF is Q = 0. 5 With the help of function table and circuit diagram explain the working of clocked SR flip flop. Draw the circuit diagrams and Truth table of all the Flip flops (SR, D, T and JK). Write a brief note on edge-triggered SR and JK Flip-Flops. Write a note on Master-Slave Flip-Flop. () Define: combinational logic circuit and sequential logic circuit. (2) With logic diagram explain the function of master-slave flip-flop. xplain D type positive edge triggered flip flop. Define the following terms: () Flip flop (2) ounter (3) Register 3 Implement T flip flop using D flip flop. 3 onvert D flip flop into SR flip flop Implement D flip flop using JK flip flop. With neat sketch design -bit bidirectional shift register. Write short note on four bit Universal Shift Register. Design a circuit for -bits parallel register with load with D Flip-Flops. Load input decides whether to load new input or to apply no change conditions. Design a synchronous D counter with JK flip-flops. Draw a frequency divider using JK FFs to divide input clock frequency by a factor of 8. 3 Design a 3-bit synchronous up counter using K-maps and positive edge-triggered JK FFs. Design -bit ripple counter using negative edge triggered JK flip flop. Design a mod-2 Synchronous up counter using D-flipflop. D Design a sequential circuit using JK Flip-Flops and two states Q0 and Q such that, () It moves to the next state for input 0. (00 to 0, 0 to 0,, to 00) (2) It moves to the previous state 9 for input. (reverse from the above mentioned steps) Design and Implement a Mod-0 asynchronous counter with T FF. Write a note on inary Ripple ounter. With logic diagram explain the operation of bit binary ripple counter. How up counter can be converted into down counter? Design a synchronous D counter with JK flip flops. Design a sequential with JK flip-flops to satisfy the following state equations: (t+) =ˊˊD+ˊˊ+D+ˊDˊ (t+) = ˊ +Dˊ+ˊˊ (t+) = D(t+) = Dˊ F Distinguish between combinational and sequential logic circuits. Give the applications of flipflops. G Give the comparison between synchronous and asynchronous counters. Give following definitions: ()State table (2) Melay machine (3) Moore machine 3 Discuss the General State machine rchitecture. 3 xplain the types of finite state machines?

5 onstruct next state table for the state diagram given in figure 6. 6 What do you mean by an output glitch problem? xplain any one method to eliminate the glitch from an OFL circuit. Draw suitable waveforms and logic diagrams. With the help of next state D input maps given in figure, construct IFL using MUXs of suitable size and number. 3 xplain the Fundamental Mode Model of synchronous State Machine with suitable example. xplain critical race problem of an asynchronous state machines with the help of one example. xplain oscillation problem of an asynchronous state machines with the help of one example. 8 9 Which TTL logic gate is used for wired NDing? ompare the Following in every aspect: TTL and MOS 3 Give definition of Totem pole output. xplain two input MOS NND gate. Write a note on Memory. ompare ROM, PL and PL. ompare the Following in every aspect: RM and ROM Define PROM Give definition of PROM. D Write short note on Programmable Logic rrays. Implement following functions using ROM. F = Σ m(, 3,, 6) F2 = Σ m(2,, 5, ) F3 = Σ m(0,, 5, ) F = Σ m(, 2, 3, ) F Write a short note on FPG. 3 3

Sample Test Paper - I

Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following: