Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space

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1 Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space Jianhua Liu, Yi Zhu, Haikun Zhu, John Lillis 2, Chung-Kuan Cheng Department of Computer Science and Engineering University of California, San Diego La Jolla, CA Department of Computer Science University of Illinois at Chicago Chicago, IL 60607

2 Outline Previous Works and Motivation Area/Timing/Power Model ILP Formulation of Prefix Adder Experimental Results Conclusions 2

3 3 Previous Works and Motivation i i i i i i b a p b a g = = Pre-processing: Post-processing: Prefix Computation: i i i i i i c p s c P G c = + = + 0 :0] [ :0] [ ] : [ ] : [ ] : [ ] : [ ] : [ ] : [ ] : [ k j j i k i k j j i j i k i P P P G P G G = + = Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Prefix network formulation:

4 Previous Works and Motivation Each output network is an alphabetical tree: Output i is the root of a binary tree covering inputs -i. An in-depth traversal of the tree terminals follows the sequence of the inputs : 3: 2: (a) j 2 3 4: 3: 2: (b) 4

5 Previous Works and Motivation : 7: 6: 5: 4: 3: 2: 8: 7: 6: 5: 4: 3: 2: 8: 7: 6: 5: 4: 3: 2: * Brent-Kung: Logical levels: 2log 2 n Max fanouts: 2 Wire tracks: Sklansky: Logical levels: log 2 n Max fanouts: n/2 Wire tracks: Kogge-Stone: Logical levels: log 2 n Max fanouts: 2 Wire tracks: n/2 * Max Fanouts is based on the regular buffer insertions at all empty space 5

6 Previous Works and Motivation Max Fanout The design space of prefix adder is considered as the tradeoff among logical levels, max fanouts and wire tracks. * Harris D, A Taxonomy of Parallel Prefix Networks Nov Logical Levels Logical levels: Max fanouts Wire tracks l + f + t Timing: L F Dgp L = log : F = 2 + t : T = 2 = log n 2 f 2 n + l (Dgp: delay of one GP adder with unit load) Wire Tracks Area: L (Hgp+T Hwt) n (Hgp: Height of one GP adder Hwt: Height of one wire track) Favor the minimal logical levels 6

7 Previous Works and Motivation Increasing impact of physical design. Power becomes a critical concern. Power Area Physical placement Detail routing Power gating Dynamic power Activity Static power Probability Logical Fanouts Levels Gate Cap Wire Cap Wire Tracks Input arrival Output Buffer time require time insertion Gate sizing Signal slope New Design Scope Timing 7

8 Previous Works and Motivation Input: bit width, physical area, input arrival times, output required times. Output: placed prefix adder Constraint: alphabetical tree rooted at each output i to cover inputs to area and timing requirements Objective: minimize power consumption 8

9 Models Area Model Distinguish physical placement from logical structure, but keep the bit-slice structure. Bit position Bit position Physical level Logical level Logical view of Brent-Kung adder Compact placement Physical view of Brent-Kung adder A = n m n: Bit width m: Physical depth 9

10 Models Timing Model Cload includes both gate and wire capacitance. Wire capacitance is proportional to wire length. C load = C wire + C gate C wire = λ w (H bb + W bb ) C gate = Σ C in (λ w = 0.5) Use a linear timing model derived from logical effort. GP l GP r Delay_GP l =.5 C load Delay_GP r = 2.0 C load W bb GP H bb logical connection bounding box real wire * Harris D, Sutherland I, Logical Effort of Carry Propagate Adders,

11 Models Power Model Total power consumption: Dynamic power + Static Power Static power: leakage current of device P sta = λ s (λ s = 0.5) Dynamic power: current switching capacitance P dyn = ρ C load ρ is the switching probability ρ = j (j is the logical level*) P total = P dyn + P sta = j C load λ s + * Vanichayobon S, etc, Power-speed Trade-off in Parallel Prefix Circuits, 2002

12 ILP on Prefix Adder Overall Picture We propose to formulate prefix computation as Integer Linear Programming (ILP) problem. Optimum solution can be produced by contemporary ILP solver. Structure variables: GP adders Connections Physical positions Capacitance variables: Gate cap Vertical wire cap Horizontal wire cap Timing variables: Input arrival time Output arrival time Power objective Structure variables defines the ILP solution space 2

13 ILP Linear Programming Linear Programming: linear constraints, linear objective, fractional variables. Maximize: x + 2 x x 3 subject to: -x + x 2 + x 3 20 x 3 x x x 0 x Constraints Solution Space Objective LP Optimal LP problems are polynomial time solvable (interior point algorithm, Karmarkar 984) 3

14 ILP Integer Linear Programming Integer Linear Programming: all variables are integers. Constraints Objective LP Optimal ILP Optimal ( nearest feasible integer solution) ILP problem with bounded variables is NP-hard. 4

15 ILP Branch and Bound Brach and bound with linear relaxation algorithm in ILP solvers: Minimize F(b, b 2, b 3, b 4, f, ) b i is binary infeasible Root (all vars are fractional) Cut b b 2 feasible (current best) Bound (Smallest candidate) infeasible b 3 b 4 It is VERY helpful if ILP objective 5 is close to LP objective

16 ILP Pseudo-Linear Constraint A constraint is called pseudo-linear if it s not effective until some integer variables are fixed. Problem: Minimize: x 3 Subject to: x 300 x x 3 = min(x, x 2 ) LP objective: 0 ILP objective: 300 ILP formulation: Minimize: x 3 Subject to: x 300 x x 3 x x 3 x 2 x 3 x 000 b () x 3 x ( b ) (2) b is binary Pseudo-linear constraints mostly arise from IF/ELSE scenarios binary decision variables are introduced to indicate true or false. 6

17 ILP Summary Integer Linear Programming is a powerful solution space search tool guided by Linear Programming. However, pseudo-linear constraints may compromise the efficiency. 7

18 ILP on Prefix Adder Structure ILP decision variables represent GP adders and interconnects in logical view. Alphabetical tree rooted at each output. Each GP adder has exact one left input and one right input. (fanin const.) At least one input is from the previous level. (logical level const.) Every GP adder roots an alphabetical tree covering a continuous segment. (root const.) 8

19 ILP on Prefix Adder Structure Variables: gp( {0,}: GP adders in the n d array (d: logical depth) wl(j,h) {0,}: The wire from (h) to the left fanin of ( wr(j,k,l) {0,}: The wire from (k,l) to the right fanin of ( Constraints: (fanin const.) One left/right fanin for each GP adder wl(j,h) = gp( ( i > h h (k,l) wr(j,k,l) = gp( ( i > k & j > l (logical level const.) At least one fanin from the previous level wl( j, j ) + wr(j,k,j ) gp( ( k 9

20 ILP on Prefix Adder Structure The segment information is necessary for root constraint. The GP segments of two children must be adjacent. Variables: gpl(, gpr( int [,n]: Constraints: The segment covered by gp( is [gpl(:gpr(] (root const.) The GP segments of two children must be adjacent gpl ( = gpl( h) if wl( j, h) = () gpr ( = gpr( k, l) if wr( j, k, l) = gpr( h) = gpl( k, l) + if wl( j, h) = & wr( j, k, l) = Conditional constraint () in ILP formulation: gpl( gpl( gpl( h) n ( wl( gpl( h) + n ( wl( j, h)) j, h)) 20

21 ILP on Prefix Adder Structure Physical position variable attached to each GP adder describes physical level. No overlap in the physical view. (overlap const.) Variables: phy( int [,m]: The physical position of gp( is (phy(). (m: physical depth) Constraints: (overlap const.) Each physical position contains at most one GP adder phy( phy( h) j h 2

22 ILP on Prefix Adder Example gp(2,)=, wl(2,,0)=, wr(2,,,0)= gp(3,2)=, wl(3,2,0)=, wr(3,2,2,)= gp(4,3)=, wl(4,3,0)=, wr(4,3,3,2)= n i n [gpl(2,):gpr(2,)] = [2:] [gpl(3,2):gpr(3,2)] = [3:] [gpl(4,3):gpr(4:3)] = [4:] j phy(2,)= phy(3,2)= phy(4,3)= d 4: 3: 2: m 4: 3: 2: Logical view Physical view 22

23 ILP on Prefix Adder Capacitance Gate capacitance is calculated based on logical fanouts. Gate cap equals to the number of fanouts, when input cap of GP adder is unit. (gate const.) Wire capacitance depends on physical placement. Vertical wire cap is proportional to the max vertical height of each fanout. (wire const.) Horizontal wire cap is proportional to the max horizontal width of each fanout. (wire const.) 23

24 ILP on Prefix Adder Capacitance Variables: Cg( float: Gate load capacitance of ( Cwv( float: Vertical wire load capacitance of ( Cwh( float: Horizontal wire load capacitance of ( Constraints: (gate const.) Gate load capacitance: Cg( wl( h, wr( k, l, = + ( k, l) (wire const.) Wire load capacitances: w Cwv( λ ( phy( h) phy( ) w Cwh( λ ( k h w Cwv( λ ( phy( k, l) phy( ) if i) if wl( h, = if (λ w = 0.5) wr( k, l, = wr( k, l, = 24

25 ILP on Prefix Adder Timing The output time is the max path delay. (output const.) Input arrival times equal to the output times of two children. (input const.) According to the timing model, gate delay is calculated based on load capacitance. Delay_GP l =.5 C load Delay_GP r = 2.0 C load

26 ILP on Prefix Adder Timing Variables: Tl( float: Left input arrival time of ( Tr( float: Right input arrival time of ( T( float [0,Tmax]: Output time of ( (Tmax: Output required time.) Constraints: (input const.) Input arrival times: Tl( = T ( h) if wl( Tr( = T ( k, l) if wr( j, k, l) = (output const.) Output time: T ( Tl( +.5 Cload( j, h) = T ( Tr( Cload( ( Cload( = Cg( + Cwv( + Cwh( ) 26

27 ILP on Prefix Adder Power Total power consumption is the summation of power consumption on each GP adder. The objective is to minimize total power consumption. Minimize : ( j Cload ( + S λ gp( 27

28 ILP on Prefix Adder Example Cg(2,)=, Cwv(2,)=0, Cwh(2,)=0.5 Cload(2,)=.5 Cg(3,2)=, Cwv(3,2)=0.5, Cwh(3,2)=0.5 Cload(3,2)=2 Cg(4,3)=0, Cwv(4,3)=0, Cwh(4,3)=0 Cload(4,3)=0 n i n 0 2 j Tl(2,)=0, Tr(2,)=0, T(2,)= =5.5 Tl(3,2)=0, Tr(3,2)=5.5, T(3,2)= =2 Tl(4,3)=0, Tr(4,3)=2, T(4,3)= = : 3: 2: d 2 4: 3: 2: m Power = Cload(2,) + 2 Cload(3,2) + 3 Cload(4,3) = 4.5 Logical view Physical view 28

29 ILP on Prefix Adder Extension Gate sizing and buffer insertion are two important optimization technologies to improve performance. Gate sizing: decrease gate delay, increase input capacitance. Buffer insertion: introduce new element, impact placement. Gate sizing and buffer insertion can be supported by ILP formulation. 29

30 Experimental Results Optimum prefix adders solved by CPLEX 9. 8-bit prefix adders Uniform input arrival time Non-uniform input arrival time Hierarchical 64-bit prefix adders 64-bit prefix adder implementation (Synopsys flow, TSMC 90nm technology) Module Compiler Astro Prime Power 30

31 Experimental Results 8-bit Uniform Method Timing Depth Power CPU Method Timing Depth Power CPU (D FO4 ) (P FO4 ) (s) (D FO4 ) (P FO4 ) (s) ILP K-S ILP ILP ILP (S) ILP ILP ILP (S) ILP (S) ILP ILP ILP (S) B-K ILP ILP ILP ILP ILP (S) Skl ILP (S) * (S): Gate sizing, B-K: Brent-Kung, Skl: Sklansky, K-S: Kogge-Stone 3

32 Experimental Results 8-bit Uniform 32

33 Experimental Results 8-bit Uniform Some typical ILP results: Fastest depth2 Fastest depth3 Fastest depth4 All the 8-bit fastest prefix adders have 4 logical levels 33

34 Experimental Results 8-bit Non-Uniform Case Power Depth Power* Depth* Increasing arrival times Decreasing arrival times Convex arrival times Increasing arrival times Decreasing arrival times Convex arrival times * Use the worst input arrival time for all inputs 34

35 Experimental Results 64-bit Hierarchical For high bit-width application, ILP method can be applied in a hierarchical design strategy. 35

36 Experimental Results 64-bit Hierarchical Hierarchical ILP designs in solution space: (The physical depth is set to 6) Method Timing Power Method Timing Power (D FO4 ) (P FO4 ) (D FO4 ) (P FO4 ) Hierarchical ILP Hierarchical ILP Brent-Kung Sklansky Hierarchical ILP Hierarchical ILP Hierarchical ILP Hierarchical ILP 5 46 Hierarchical ILP Kogge-Stone Hierarchical ILP Hierarchical ILP

37 Experimental Results 64-bit Hierarchical The power of Kogge-Stone add is much 37 larger than other prefix adders.

38 Experimental Results 64-bit Hierarchical The fastest 64-bit hierarchical ILP adder: ( 8) ( 8) Hierarchical ILP level (Physical view) Hierarchical ILP level 2 (Physical view) 38

39 Experimental Results 64-bit Implementation 64-bit ILP prefix adders compared with 64-bit fast prefix adders generated by Module Compiler with relative placement. ILP Module Compiler Power Timing (ns) Total Power [Wire Power] (mw) Timing (ns) Total Power [Wire Power] (mw) Saving [Wire] (%) [0.93] [2.8] 6% [67%] [0.90] [2.] 49% [57%].3.5 [0.65] [.5] 50% [57%] 39

40 Experimental Results 64-bit Implementation 64-bit ILP Prefix Adder Physical View 64-bit MC Prefix Adder Physical View 40

41 Conclusions We propose an ILP method to solve minimal power prefix adders. The comprehensive area/timing/power model involves physical placement, gate/wire capacitance and static/dynamic power consumption. The ILP method can handle gate sizing, buffer insertion for both uniform and non-uniform input arrival time applications. The ILP method can be applied in hierarchical design methodology for high bit-width applications. 4

42 42

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng Department of Computer Science and Engineering University of California, San