Problems in VLSI design

Transcription

1 Problems in VLSI design wire and transistor sizing signal delay in RC circuits transistor and wire sizing Elmore delay minimization via GP dominant time constant minimization via SDP placement problems quadratic and l 1 -placement placement with timing constraints 1

2 Signal delay in RC circuit 1 v in v k v in 0.5 t = 0 D k C dv dt = G(v(t) 1), v(0) = 0 capacitance matrix C = C T 0 conductance matrix G = G T 0 Problems in VLSI design 2

3 v: node voltages as t, v(t) 1 delay at node k: D k = inf{t v k (t) 0.5 for t T } critical delay: D = max k D k Problems in VLSI design 3

4 Transistor sizing RC model of transistor G S R sd 1/w D drain C g w C s w C d w gate RC model (on) source G S D nmos transistor (width w) C g w C s w RC model (off) C d w Problems in VLSI design 4

5 example v out CL Problems in VLSI design 5

6 to first approximation: linear RC circuit design variable: transistor width w drain, source, gate capacitance affine in width on resistance inversely proportional to width Problems in VLSI design 6

7 Wire sizing interconnect wires in IC: distributed RC line lumped RC model: l i w i R i l i /w i C i w i l i C i replace each segment with π model segment capacitance proportional to width Problems in VLSI design 7

8 segment resistance inversely proportional to width design variables: wire segment widths w i Problems in VLSI design 8

9 Optimization problems involving delay C(x) dv dt = G(x)(v(t) 1), v(0) = 0 design parameters x: transistor & wire segment widths capacitances, conductances are affine in x: C(x) = C 0 + x 1 C x m C m G(x) = G 0 + x 1 G x m G m Problems in VLSI design 9

10 tradeoff between delay, complicated function of x area, affine in x dissipated power in transition v(t) = 0 1 affine in x 1 T C(x)1 2 Problems in VLSI design 10

11 Elmore delay area above step response T elm k = 0 (1 v k (t))dt first moment of impulse response T elm k = 0 tv k (t) dt Problems in VLSI design 11

12 placements 1 v k T elm k v k 0.5 D k D k T elm k T elm k 0.5D k good approximation of D k only when v k is monotonically increasing interpret v k as probability density: T k is mean, D k is median Problems in VLSI design 12

13 RC tree Elmore delay for RC tree R 2 R R 1 C 2 C 3 v in 1 R 4 R 5 4 R 6 5 C 6 C 1 6 C 4 C 5 one input voltage source resistors form a tree with root at voltage source all capacitors are grounded Problems in VLSI design 13

14 Elmore delay to node k: ( ) C i R s upstream from node k and node i i R 2 2 R 3 3 v in R 1 C 1 1 C 2 C 3 R 4 R 5 4 R C 5 C 4 C 6 Example: T elm 3 = C 3 (R 1 + R 2 + R 3 ) + C 2 (R 1 + R 2 ) + C 1 R 1 + C 4 R 1 + C 5 R 1 + C 6 R 1 Problems in VLSI design 14

15 Elmore delay optimization via GP in transistor & wire sizing, R i = α i /x i, C j = a T j x + b j (α i 0, a j,b j 0) Elmore delay: T elm k = ij γ ij R j C i = k=1 β k m i=1 x α ik i (γ ij = +1 or 0, β k 0, α ij = +1,0, 1)... a posynomial function of x 0 hence can minimize area or power, subject to bound on Elmore delay using geometric programming commercial software (1980s): e.g., TILOS Problems in VLSI design 15

16 Limitations of Elmore delay optimization not a good approximation of 50% delay when step response is not monotonic (capacitive coupling between nodes, or non-diagonal C) no useful convexity properties when there are loops of resistors circuit has multiple sources resistances depend on more than one variable Problems in VLSI design 16

17 Dominant time constant C(x) dv dt = G(x)(v(t) 1), v(0) = 0 eigenvalues 0 > λ 1 λ 2 λ n given by det(λ i C(x) + G(x)) = 0 solutions have form v k (t) = 1 i α ik e λ it slowest ( dominant ) time constant given by T dom = 1/λ 1 (related to delay) Problems in VLSI design 17

18 1/T dom can bound D, T elm in terms of T dom in practice, T dom is good approximation of D Problems in VLSI design 18

19 Dominant time constant constraint as linear matrix inequality upper bound T dom T max 1/T dom 1/T max T dom T max T max G(x) C(x) 0 convex constraint in x (linear matrix inequality) Problems in VLSI design 19

20 no restrictions on G, C T dom is quasiconvex function of x, i.e., sublevel sets { x T dom (x) T max } are convex Problems in VLSI design 20

21 Sizing via semidefinite programming minimize area, power s.t. bound on T dom, upper and lower bounds on sizes minimize f T x subject to T max G(x) C(x) 0 x min i x i x max i a convex optimization problem (SDP) no restrictions on topology (loops of resistors, non-grounded capacitors) Problems in VLSI design 21

22 Wire sizing minimize wire area subject to bound on delay (dominant time constant) bounds on segments widths RC-model: x i x 1 x 20 βx i αx i βx i Problems in VLSI design 22

23 as SDP: minimize l i x i i subject to T max G(x) C(x) 0 0 x i 1 Problems in VLSI design 23

24 area-delay tradeoff Tdom (d) (c) (b)(a) wire area globally optimal tradeoff curve optimal wire profile tapers off Problems in VLSI design 24

25 step responses (solution (a)) voltage D T dom T elm time Problems in VLSI design 25

26 Wire sizing and topology x 3 x i x 1 x x 5 β i x i αx i β i x i x 4 not solvable via Elmore delay minimization min area s.t. max dominant time constant (via SDP): 4 x 6 xi minimize subject to T max G(x) C(x) 0 Problems in VLSI design 26

27 tradeoff curve dominant time constant (c) (b) (a) area usually have more wires than are needed Problems in VLSI design 27

28 solutions usually have some x i = 0 different points on tradeoff curve have different topologies Problems in VLSI design 28

29 solution (a) v 1 (t) 1 v 4 (t) v 3 (t) x 4 = 0.15 x 6 = D T dom T elm Problems in VLSI design 29

30 solution (b) x 3 = 0.02 v 1 1 (t) v 4 (t) v 3 (t) x 4 = 0.03 x 6 = T dom T elm D Problems in VLSI design 30

31 solution (c) x 3 = v 1 (t) v 3 (t) D T dom T elm Problems in VLSI design 31

32 Placement list of cells: cells i = 1,...,N are placeable, cells i = N + 1,...,N + M are fixed (e.g., I/O) input and output terminals on boundary of cells group of terminals connected together is called a net Problems in VLSI design 32

33 Problems in VLSI design 33

34 placement of cells determines length of interconnect wires, hence signal delay problem: determine positions (x k,y k ) for the placeable cells to satisfy delay constraints practical problem sizes can involve 100,000s of cells exact solution (including delay, area, overlap constraints) is very hard to compute heuristics (often based on convex optimization) are widely used in practice Problems in VLSI design 34

35 Quadratic placement assume for simplicity: cells are points (i.e., have zero area) nets connect two terminals (i.e., are simple wires) quadratic placement: minimize nets (i,j) w ij ( (xi x j ) 2 + (y i y j ) 2) weights w ij 0 unconstrained convex quadratic minimization (called quadratic programming in VLSI) Problems in VLSI design 35

36 solved using CG (and related methods) exploiting problem structure (e.g., sparsity) physical interpretation: wires are linear elastic springs widely used in industry constraints handled using heuristics (e.g., adjusting weights) Problems in VLSI design 36

37 l 1 -placement minimize nets (i,j) w ij ( x i x j + y i y j ) measures wire length using Manhattan distance (wire routing is horizontal/vertical) motivation: delay of wire (i,j) is RC with R = R driver + R wire, C = C wire + C load R driver, C load are given, R wire R driver, C wire wire length (Manhattan) Problems in VLSI design 37

38 R driver C wire C load called linear objective in VLSI Problems in VLSI design 38

39 Nonlinear spring models minimize nets (i,j) h( x i x j + y i y j ) h convex, increasing on R + example h(z) z flat part avoids clustering of cells Problems in VLSI design 39

40 quadratic part: for long wires R wire length solved via convex programming Problems in VLSI design 40

41 Timing constraints cell i has a processing delay D proc i propagation delay through wire (i,j) is αl ij, where l ij is the length of the wire minimize max delay from any input to any output Problems in VLSI design 41

42 D proc 1 l 14 D proc 4 l 45 l 13 D proc 3 l 35 D proc 5 D proc 2 l 23 Problems in VLSI design 42

43 problem is: minimize subject to T cells in path D proc i + wires in path αl ij T one constraint for each path variables: T, positions of placeable cells (which determine l ij ) a very large number of inequalities Problems in VLSI design 43

44 A more compact representation introduce new variable T out i for each cell for all cells j, add one inequality for each cell i in the fan-in of j T out i + αl ij + D proc j T out j (1) for all output cells T out i T (2) minimize T subject to (??) and (??) convex optimization problem: with l 1 -norm, get LP with l 2 -norm, get SOCP Problems in VLSI design 44

45 extensions (still convex optimization): delay is convex, increasing fct of wire length max delay constraints on intermediate cells different delay constraints on cells Problems in VLSI design 45

46 Non-convex constraints and generalizations non-convex constraints cells are placed on grid of legal positions cells are rectangles that cannot overlap reserved regions on chip Problems in VLSI design 46

47 generalizations multi-pin nets: share interconnect wires combine placement with wire and gate sizing Problems in VLSI design 47