! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.


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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission lines arise? " Lossless Transmission Line " Termination " Lossy Transmission Line 2 Capacitance Crosstalk! There are capacitors everywhere! Already talked about " Wires modeled as a distributed RC network " Parasitic capacitances between terminals on transistor 3 4 Capacitance Everywhere Capacitance! Potentially a capacitor between any two conductors " On the chip " On the package " On the board! decrease with conductor separation! increase with size! depends on dielectric! All wires " Package pins " PCB traces " Cable wires " Bit/word lines C = ε r ε 0 A d 5 6 1
2 Wire Capacitance Crosstalk! Changes in voltage on one wire may couple through parasitic capacitance to an adjacent wire! A capacitor does not like to change its voltage instantaneously! A wire has high capacitance to its neighbor. " When the neighbor switches from 1> 0 or 0>1, the wire tends to switch too. " Called capacitive coupling or crosstalk.! Crosstalk effects " Noise on nonswitching wires " Increased delay on switching wires 7 Slide 8 Driven Wire Qualitative! What happens to a driven neighbor wire? " One wire switches " Neighbors driven but not switch " What happens to neighbors? 10 Driven Wire Undriven Wire! Can this be a problem?! What if neighbor is:! What happens to undriven wire?! Where do we have undriven wires? " Clock line " Asynchronous control " Nonclock used in synchronous system " Outputs sampled at clock edge
3 Clocked Logic! CMOS driven lines! Clocked logic " Willing to wait to settle Quantitative! Impact is on delay " May increase delay of transitions 13 Wire step response Undriven Adjacent Wire! Step response for isolated wire?! V 1 transitions from 0 to V " How big is the noise on V 2? Undriven Adjacent Wire Undriven Adjacent Wire! V 1 transitions from 0 to V " How big is the noise on V 2? I(t) = C dv(t) dt! V 1 transitions from 0 to V " How big is the noise on V 2? I(t) = C dv(t) dt d(v C 1 (t) V 2 (t)) dv 1 = C 2 (t) 2 dt dt dv C 1 (t) 1 = (C 1 + C 2 ) dv (t) 2 dt dt C 1 V 1 (t) = (C 1 + C 2 )V 2 (t) V 2 (t) = V 1 (t) C 1 + C C 1 3
4 SPICE C 1 =10pF, C 2 =20pF Good (?) Capacitance! High capacitance to ground plane " Limits node swing from adjacent conductors " C V 2 = 1 $ ' V # C 1 + C 1 2 & Driven Adjacent Wire Driven Adjacent Wire! What happens when neighbor line is driven?! What happens when neighbor line is driven? " Recovers with time constant: R 2 (C 1 +C 2 ) Spice: R 2 =1K, C 1 =10pF, C 2 =20pF Magnitude of Noise on Driven Line! Magnitude of diversion depends on relative time constants " τ 1 << τ 2 " full diversion, then recover " τ 1 >> τ 2 " Drive capacitor faster than line 1 can change diversion " τ 1 ~= τ 2 " little noise " Somewhere in between
5 Spice: C 1 =1pF, C 2 =2pF Switching Line with Finite Drive! What impact does the presence of the non switching line have on the switching line? " All previous questions were about nonswitching " Note R on switching Simultaneous Transition Simultaneous Transition! What happens if lines transition in opposite directions?! What happens if transition in opposite directions? " Must charge C 1 by 2V " Or looks like 2C 1 between wires Simultaneous Transition Simulation! What happens if lines transition in same direction?! V 2 switching at ¼ frequency of V 1! No crosstalk reference case where no V
6 Simulation Setup Crosstalk Simulation V1 V2 C1 C2 C2 1.3ns 1.8ns 2.8ns Crosstalk Simulation Crosstalk Simulation 1.3ns 1.8ns 2.8ns 1.3ns 1.8ns 2.8ns Cables and PCB Wires Where Does it Arise? Source;
7 Printed Circuit Board Interconnect Cross Section Source: 37 Standard Cell Area Noise Implications!! All cells uniform height Penn ESE 570 Spring Khanna Width of channel determined by routing! "! 39 But glitches cause extra delay Also cause extra power from false transitions Dynamic logic never recovers from glitches "! Wire Engineering! " Can t correct midcycle, need precharge Memories and other sensitive circuits also can produce the wrong result (i.e faults) Slide 40 Wire Engineering Goal: achieve delay, area, power goals with acceptable noise Degrees of freedom:!! Goal: achieve delay, area, power goals with acceptable noise Degrees of freedom: " " " Width Spacing Layer Coupling:2Cadj / (2C adj+cgnd) Cell area! So what if we have noise? If the noise is less than the noise margin, nothing happens Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes Delay (ns):rc/2 inv nand w s Pitch (nm) WireSpacing (nm) Pitch (nm) l t h Slide 41 Slide 42 7
8 Wire Engineering! Goal: achieve delay, area, power goals with acceptable noise! Degrees of freedom: " Width " Spacing " Layer " Shielding Delay (ns): RC/ Pitch (nm) Coupling: 2C adj / (2C adj +nd ) Pitch (nm) Wire Spacing (nm) Repeaters in Wiring vdd a 0 a 1 gnd a 2 vdd a 0 a 1 gnd a 2 a 3 vdd gnd a 0 b 1 vdd b 0 a 1 a 2 b 2 Slide 43 Reminder: Wire Delay Interconnect Buffering! Wire N units long: =R unit *C unit *N 2 /2! With " R unit =1kΩ " C unit =1pF R wire = N R unit = N C unit! RC (onchip) Interconnect Buffering Penn ESE 570 Spring Khanna Delay of Wire Formulate Delay! Long Wire: 1mm! R u = 60K Ω per 1mm of wire! C u = 0.16 pf per 1mm of wire! Driven by buffer " = 25K Ω " C self = 0.02 ff " = 0.01fF! Loaded by identical buffer Delay of buffer driving wire?
9 Formulate Delay Calculate Delay! C load =! =! C self =! =! R wire = Delay of buffer driving wire? + + C load ) + 0.5R wire C load + + C load ) + 0.5R wire C load Calculate Delay Calculate Delay! C load = 2 =.02fF! = 25K Ω! C self = 0.02fF! = L*C u =.16pF! R wire = L*R u = 60K Ω! C load = 2 =.02fF! = 25K Ω! C self = 0.02fF! = L*C u =.16pF! R wire = L*R u = 60K Ω 8.8ns + + C load ) + 0.5R wire C load + + C load ) + 0.5R wire C load 4ns + 4.8ns +1.2ps Buffering Wire Buffering Wire: L/2! C load =! =! C self =! =! R wire =
10 Buffering Wire: L/2! C load = 2 =.02fF! = 25K Ω! C self =.02fF! = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω Buffering Wire: L/2! C load = 2 =.02fF! = 25K Ω! C self =.02fF! = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω + + C load ) + 0.5R wire C load 2ns +1.2ns +.6ps = 3.2ns Buffering Wire: L/2 Buffering Wire: L/N! C load = 2 =.02fF! = 25K Ω! C self =.02fF! = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω 6.4ns Wire of Length Delay (ns) Number in 1mm Total Delay for 1mm (ns) 1 mm 8.8ns 1 8.8ns 0.5mm 3.2ns 2 6.4ns 0.1mm C load ) + 0.5R wire C load 2ns +1.2ns +.6ps = 3.2ns 0.01 mm mm C load ) + 0.5R wire C load Buffering Wire: L/N N Buffers! Delay Equation for N buffers? Wire of Length Delay (ns) Number in 1mm (N) Total Delay for 1mm (ns) 1 mm 8.8ns 1 8.8ns 0.5mm 3.2ns 2 6.4ns N C self + N +C load R wire N N N C load 0.1mm 0.45ns ns 0.01 mm.041ns ns mm.005ns ns + + C load ) + 0.5R wire C load
11 Minimize Delay! Minimize delay! Derivative with respect to N and solve for 0 N ( C self +C load ) R N wire C load 0 = ( C self +C load ) R N 2 wire Minimize Delay Equalizes delay in buffer and wire N = 0.5R wire C self + C load ( ) N R ( buf C self + C ) + R C + 0.5! 1 $ load # buf wire " N &R wire C load N = 0.5R wire ( C self +C load ) Delay with Optimal N Segment Length 0.5R wire C self + C load ( ) ( C self + C load ) ! # # " C self + C $ ( load ) & 0.5R wire & R C + R wire wire load 0.5R wire ( ( C self + C load )) R wire ( ( C self + C load )) C load 2 0.5R wire ( ( C self + C load )) + C load 63! R wire = L R unit! = L C unit * L seg * L seg = L N # & R N = 0.5 wire ( $ + C load )( ' # & R N = L 0.5 u C u ( $ + C load )( ' ( ) = L " N = 2 C self + C load $ # R u C ' u & 64 Optimal Segment Length! Delay scales linearly with distance once optimally buffered * L seg ( ) = L # N = 2 C self + C & load ( R u C $ u ( ' # & R N = L 0.5 u C u ( $ + C load )( ' Buffer Size?! How big should buffer be? " = R un /W " C self = 2 W C dff = 2 W γ " C load = 2 W
12 Buffer Size? Implication on Buffer Size  W! How big should buffer be? " = R un /W! R wire = L R unit! = L C unit " C self = 2 W C dff = 2 W γ " C load = 2 W 2 0.5R wire ( ( C self + C load )) + C load! R 2 0.5R wire C un wire W 2WC $ # ( g ( 1+γ) )& + R un " W 2W 2 0.5R wire ( 2R un ( 1+γ) ) + R un W 2W 0 = 2R wire R un 1 W 2 W = R un 2R wire = R un C unit 2R unit 2 0.5R wire ( 2R un ( 1+γ) ) + R un W 2W! # W independent of Length " Depends on technology Delay at Optimum W Delay at Optimum W 2 0.5R wire ( 2R un ( 1+γ) ) + R un W 2W 2 0.5R wire ( 2R un ( 1+γ) ) + R un R un 2R wire 2 R un 2R wire 2 0.5R wire ( 2R un ( 1+γ) ) + R un 2R wire + R un 2R wire 2 0.5R wire ( 2R un ( 1+γ) ) + 2 2R un R wire! If γ=1 2 R wire ( R un ( 1+1) ) + 2 2R un R wire 2 2R un R wire + 2 2R un R wire 4 2R un R wire! Optimal design equalizes all delays! Transmission Lines Where Transmission Lines Arise! Cable: coaxial! PCB " Strip line " Microstrip line! Twisted Pair (Cat5)
13 Transmission Lines! This is what wires/cables look like " Aren t an ideal equipotential Wire Formulation " Signals do take time to propagate " Maintain shape of input signal " Within limits " Shape and topology of wiring effects how signals propagate! Need theory/model to support design " Reason about behavior " Understand what can cause noise " Engineer high performance/speed communication Wires RC Wire! In general, our wires have distributed R, L, C components! When R dominates L " We have the distributed RC Wires " Typical of onchip wires in ICs Lossless Transmission Line Intuitive: Lossless! When resistance is negligible! Pulses travel as waves without distortion " Have L = Lossless Transmission Line " (up to a characteristic frequency) " No energy dissipation (loss) through R s " More typical of Printed Circuit Board wires and bond wires
14 SPICE Simulation Step Response SPICE Pulse Response SPICE Contrast RC Wire Contrast Model! Now voltage is a function of time and position " Position along wire distance from source! Want to get V(x,t) " And I(x,t)
15 Implication Propagation Rate in Example " Wave equation: " Solution: 2 V x = LC 2 V t V(x,t) = A + Be x wt! L=1uH! C=1pF! What is w? w = 1 LC " What is w? Be x wt = LCw 2 Be x wt w = 1 LC w is the rate of propogation Signal Propagation Signal Propagation Delay linear in length Contrast RC Wire Impedance R delay quadratic in length.5r un C un N 2! Transmission lines have a characteristic impedance Z 0 = L C
16 Infinite Lossless Transmission Line! Transmission line looks like resistive load Z 0 = L C Termination Z 0! Input waveform travels down line at velocity " Without distortion w = 1 LC 91 End of Line! What happens at the end of the transmission line? Analyze End of Line! Incident Wave, Reflected Wave, Transverse Wave End of Line! What happens at the end of the transmission line? " Short Circuit, R=0 " Hint: what must happen in steady state? " Terminate with R=Z 0 " Open Circuit, R= Reflection Reflection coefficient # R Z V 0 & i ( = V $ R + Z r 0 '
17 Analyze End of Line Open! V i +V r =V t " R Z V 0 i $ ' = V r # R + Z 0 & " R Z V 0 i $ ' = V t V i # R + Z 0 & " R Z V 0 i $ +1' = V t # R + Z 0 & " 2R Transmission coefficient V i $ ' = V t # R + Z 0 & # R Z V 0 & i ( = V $ R + Z r 0 ' Terminate R=Z 0 Short # R Z V 0 & i ( = V $ R + Z r 0 ' # R Z V 0 & i ( = V $ R + Z r 0 ' Longer LC (open) Pulse Travel RC! 40 Stages! L=100nH! C=1pF w = 1 LC = c 0 ε r µ r Stage delay? How long to propogate?! V1,V3,V4,V5,V6 about 10 stages apart! Drive with 2ns Pulse! No termination (open circuit) " What reflection do we expect?
18 Visualization! Back to Source Matched Open Short Back at Source? R Z 0! What happens at source?! What happens? " Depends on how it s terminated " 75 Ω termination on 50 Ω line Transmission Line Symbol Simulation! Specify delay of full Tline and characteristic impedance! Need reference! For these, with direct drive from voltage source " Source looks like short circuit (not typical of CMOS) " Source cannot be changed
19 50Ω line, 75Ω termination Source Series Termination! What happens here? # R Z V r = V 0 & # 75 50& i ( = V $ R + Z i ( = 0.2V 0 ' $ ' i Simulation Series Termination! R series = Z 0! Initial voltage divider " Half voltage pulse propogates down Tline! End of line open circuit " Sees single transition to full voltage (full reflection)! Reflection returns to source and sees termination R series = Z 0! No further reflections CMOS Driver / Receiver CMOS Driver! Driver: What does a CMOS driver look like at the source? " I d,sat 45nm, V dd =1V! Receiver: What does a CMOS inverter look like at the sink?! Driver: What does a CMOS driver look like at the source? " I d,sat 45nm, V dd =1V " Min size: " I drive =1200µA/µm*45nm=54µA " R out =V dd /I drive =18kΩ
20 CMOS Driver CMOS Receiver! Driver: What does a CMOS driver look like at the source? " I d,sat 45nm, V dd =1V " Min size: " I drive =1200µA/µm*45nm=54µA " R out =V dd /I drive =18kΩ " W=370 " I drive =1200µA/µm*45nm*370=20mA " R out =V dd /I drive =50Ω! Receiver: What does a CMOS inverter look like at the sink? Lossy Transmission Line Lossy Transmission Line! How do addition of R s change? " Concretely, discretely think about R=0.2Ω every meter on Z 0 =100Ω " what does each R do?! Each R is a mismatched termination! Each R is a voltage divider " 2(R + Z V t = V 0 ) i $ ' #(R + Z 0 ) + Z 0 & " Z V i+1 = V 0 t $ ' # R + Z 0 & Lossy Transmission Line Lossy Transmission Line " 2(R + Z V i+1 = V 0 ) " Z 0 i $ ' $ ' #(R + Z 0 ) + Z 0 &# R + Z 0 & "" 2(R + Z V snk = V 0 ) " Z 0 src $ $ ' $ '' ##(R + Z 0 ) + Z 0 &# R + Z 0 && N! How long before drop voltage by half? R=0.2Ω every meter on Z 0 =100Ω "" 2(R + Z V snk = V 0 ) " Z 0 src $ $ ' $ '' ##(R + Z 0 ) + Z 0 &# R + Z 0 && N
21 Idea! Capacitance is everywhere, especially between adjacent wires, and will get noise from crosstalk " Clocked and driven wires " Slow down transitions " Undriven wires voltage changed " Can cause spurious/false transitions! Wire delay linear once buffered optimally " Optimal buffering equalizes delays " Buffer delay, Delay on wire between buffers, Delay of wire driving buffer! Transmission lines " highspeed " high throughput " longdistance signaling! Termination Admin! Tania extra office hours " Monday 13pm! Tuesday (last) lecture " Details about final exam " Review for final exam
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