VLSI Design and Simulation

Transcription

1 VLSI Design and Simulation Performance Characterization

2 Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation

3 Performance Characterization Inverter Voltage Transfer Curve V out V DD V DD V in

4 Performance Characterization Voltage versus Time curve (ideal) V in V DD V out time

5 Performance Characterization Gate delay Voltage versus Time curve V in V DD V out time

6 Performance Characterization Interconnect delay V 1 V 2 V DD V 1 V 2 time

7 Performance Characterization Delay Primary determinant of the speed of a circuit Due to resistances and capacitances Intrinsic resistance and capacitance Extrinsic resistance and capacitance

8 Resistance Estimation Dependent on resistivity of material Directly proportional to length Inversely proportional to cross-sectional area R = ρ l A

9 Resistance Estimation R = ρ L A = ρ H L W = R S L W H W L

10 Resistance Estimation R S is the sheet resistance expressed in terms of Ω/ H W L H 2W 2L

11 Resistance Estimation Interconnect Material Typical Resistance (Ω/( ) Top metal Polysilicon Diffusion

12 Resistance Estimation Intrinsic resistance In linear region I DS = k ( V GS V T )V DS V 2 DS 2 R eq = R S = 1 k( V GS V T ) = 1 W µc ox L V V GS T 1 µc ox ( V GS V T ) ( ) = 1 ( ) µc ox V GS V T L W

13 Resistance Estimation Intrinsic resistance Dependent on C ox and carrier mobility Temperature variant Typically Ω/

14 Capacitance Estimation Capacitance in concert with interconnect resistance is the primary determinant of interconnect delays Intrinsic capacitance Interconnect capacitances

15 MOS device capacitances Overlap related capacitance Channel related capacitances Dependent on region of operation Diffusion to substrate capacitances

16 MOS device capacitances Gate Source Drain C GSO C GDO n+ C GCS C GCD n+ C GCB C SB C DB

17 MOS device capacitances C GCD C GCS C GCB C SB C DB

18 MOS device capacitances Overlap related capacitance C GSO = C DSO = ε ox t ox A overlap = C ox x D W Usually can be ignored since x D is very small

19 MOS device capacitances Channel related capacitances Cutoff No channel Therefore, no gate to source or drain capacitances

20 MOS device capacitances Gate Source Drain n+ C 0 C GCB = C 0 C dep C dep n+ C 0 = C ox WL C dep = ε silicon d C 0 + C dep WL

21 MOS device capacitances Channel related capacitances Cutoff No channel Therefore, no gate to source or drain capacitances As gate voltage increases, depletion region deepens, causing C dep to decrease, and thus decrease the gate to body capacitance As gate voltage nears V T, inversion channel forms causing a barrier for the gate to body capacitance

22 MOS device capacitances C gb C 0 C 0 C dep C 0 + C dep V t V gs

23 MOS device capacitances Channel related capacitances Saturation Channel is pinched off Gate to source capacitance exists Gate to drain capacitance is zero C GCB = 2 3 C ox WL C GCD = 0

24 MOS device capacitances Channel related capacitances Linear Channel is formed Therefore, no gate to body capacitance C GCS = C GCD = C ox WL 2

25 MOS device capacitances C GCB C GCS C GCD C 0 C dep C 0 C 0 + C dep 2 3 C C 0 V t V DS + V t V gs

26 MOS device capacitances C g C C 0 C 0 C dep C 0 + C dep V t V DS + V t V gs

27 MOS device capacitance Channel related capacitance Worst case C g = C ox WL C ox ox ranges from ff/µm 2 For a 1.5µ by 1.5µ channel C g = (6)(1.5)(1.5) =13.5 ff

28 MOS device capacitances Diffusion to substrate capacitance Junction capacitance L S W C diff = C j L S W C j is the bottom-plate capacitance per area

29 MOS device capacitances Side wall or periphery capacitance (drain and source sidewalls) L S L W C diff = C jsw (2L S + W ) C jsw is the side wall capacitance per linear distance

30 MOS device capacitances C j is typically.5-2 ff/µm 2 C jsw is typically ff/µm For a 1.5µ by 1.5µ diffusion region C diff = C j L S W + C jsw (2L S + W ) = 2(1.5)(1.5) +.28( ) = 5.8 ff

31 Interconnect capacitances W H L t di C plate = ε di t di WL

32 Interconnect capacitances t h w When h is comparable in magnitude to t, fringing electric fields can increase the total effective parasitic capacitance The effect is magnified as the ratio of w to h decreases If w=h, the effective capacitance can be up to 10 times C plate

33 Cross-Interconnect capacitances Can be very difficult to compute Requires three dimensional field simulations Usually provided by process measurements

34 Cross Interconnect Capacitances.25µm m process Area (ff( ff/µm 2) Perimeter (ff( ff/µm ) Poly over oxide Metal1 over oxide Metal2 over oxide Metal1 over poly Metal2 over poly Metal2 over Metal

35 Interconnect capacitances Can dominate the effect of the gate capacitance Example: 100µm m metal1 line over oxide Area capacitance: 100µm m x 1µm 1 m x.030ff/µm 2 = 3 ff Fringing capacitance: 100µm m x 2 x.040ff. 040fF/µm m = 8.08 ff Total capacitance: 11 ff

36 Inductance For the most part is not an issue Wire inductance is on the order of 10s of ph per mm Small enough to ignore except for very high performance chips Inductance is usually higher for I/O interfaces

37 Delay Definitions V OH (V OH + V OL )/2 V OL time V OH V 90% t f t r (V OH + V OL )/2 V 10% t dhl t dlh time

38 Interconnect delay V in R V out Lumped RC model C Charge V in to V DD The transient output voltage is V out(t) = V DD 1 e V DD 2 = V DD 1 e t dlh RC t dlh RC = ln 1 2 t dlh.69rc t RC

39 Interconnect delay Distributed RC ladder model R/N R/N R/N R/N V in V out C/N C/N C/N C/N More accurate than lumped RC model More difficult to solve for large N Need full-scale SPICE simulation

40 Elmore Delay Single line model not useful for generalized RC tree networks R 4 C 4 V in R 1 R 2 R 3 C 1 C 2 C 3

41 Next class More Performance Characterization