Delay and Power Estimation


 Aubrey Ford
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1 EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What if? he step response usually looks like a 1 st order response with a decaying eponential Use delay models to estimate delay = total capacitance on output node Use effective resistance So that t pd = haracterize transistors by finding their effective Depends on average current as gate switches EEN
2 Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance, capacitance Unit pmos has resistance, capacitance apacitance proportional to width esistance inversely proportional to width g d k s g d /k k s k k g d k s g s k /k k k d EEN Effective esistance Shockley models have limited value Not accurate enough for modern transistors oo complicated for much hand analysis Simplification: treat transistor as resistor eplace I ds (V ds, V gs ) with effective resistance I ds = V ds / averaged across switching of digital gate oo inaccurate to predict current at any given time But good enough to predict delay EEN
3 apacitance Values = g = s = d = ff/m of gate width Values similar across many yprocesses esistance 6 K*m in 0.6um process Improves with shorter channel lengths Unit transistors t May refer to minimum contacted device (4/ ) Or maybe 1 m wide device Doesn t matter as long as you are consistent EEN Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter 1 1 EEN
4 Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter 1 1 EEN Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter 1 1 EEN
5 Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter 1 1 d = 6 EEN Eample: input NND Sketch a input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (). EEN
6 Eample: input NND Sketch a input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (). EEN Eample: input NND Sketch a input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (). EEN
7 input NND aps nnotate the input NND gate with gate and diffusion capacitance. EEN input NND aps nnotate the input NND gate with gate and diffusion capacitance. EEN
8 input NND aps nnotate the input NND gate with gate and diffusion capacitance EEN Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as ladder Elmore delay of ladder t pd itosource i nodes i N N N 1 N EEN
9 Eample: input NND Estimate worstcase rising and falling delay of input NND driving h identical gates. B h copies EEN Eample: input NND Estimate rising and falling propagation delays of a  input NND driving h identical gates. B 6 4h h copies EEN
10 Eample: input NND Estimate rising and falling propagation delays of a  input NND driving h identical gates. B 6 4h h copies (6+4h) t pdr EEN Eample: input NND Estimate rising and falling propagation delays of a  input NND driving h identical gates. B 6 4h h copies t 64 (6+4h) pdr h Note: he cap at node is neglected for simplicity. It shall be considered for more accurate analysis more on this later. EEN
11 Eample: input NND Estimate rising and falling propagation delays of a  input NND driving h identical gates. B 6 4h h copies EEN Eample: input NND Estimate rising and falling propagation delays of a  input NND driving h identical gates. B 6 4h h copies / / (6+4h) tpdf EEN
12 Eample: input NND Estimate rising and falling propagation delays of a  input NND driving h identical gates. B 6 4h h copies / / (6+4h) pdf h t h EEN Delay has two parts Parasitic delay 6 or 7 Delay omponents Independent of load Effort delay 4h Proportional to load capacitance EEN
13 ontamination Delay Bestcase (contamination) delay can be substantially less than propagation delay. E: If both inputs fall simultaneously B 6 4h (6+4h) tcdr h EEN Dynamic vs Static iming nalysis Dynamic timing analysis Simulation Depends on input stimulus vectors Do not report timing on false paths With large number of testing vectors ccurate Slow Static timing analysis Fast onsider all paths Pessimism by considering false paths which are never eercised EEN
14 Eample of Static iming nalysis 7/4/ 5// 9/6/ 11 4/7/ 4 0/17/ 7 18/18/0 /0/ 8/8/0 11/11/0 rrival time: input > output, take ma equired arrival time: output > input, take min Slack = required arrival time arrival time EEN Power and Energy Power is drawn from a voltage source attached to the V pin(s) of a chip. Instantaneous Power: Energy: verage Power: Pt () i () tv E P() t dt i () t V dt E 1 P avg i() t Vdt EEN
15 Dynamic Power Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = V is required On falling output, charge is dumped to GND his repeats f sw times over an interval of V i (t) f sw EEN Dynamic Power ont. 1 P dynamic i () t V dt V 0 0 i () t dt V fswv V f sw ount the number of rising transitions at the output: trigged by the falling transitions of the input with a frequency same as the input frequency. V i (t) f sw EEN
16 ctivity Factor Suppose the system clock frequency = f Let f sw = f, where = activity factor If the signal is a clock, = 1 If the signal switches once per cycle, = ½ Dynamic gates: Switch either 0 or times per cycle, = ½ Static gates: Depends on design, but typically = 0.1 Dynamic power: P V f dynamic EEN Short ircuit urrent When transistors switch, both nmos and pmos networks may be momentarily ON at once Leads to a blip of short circuit current P s (V dd V t ) t r f p ssume t r = t f for the input f p : frequency of the input See Weste & Eshraghian, nd edition V out Input falling V out < 10% of dynamic power if rise/fall times are comparable for input and output Input rising EEN
17 Static Power Static power is consumed even when chip is quiescent. Leakage draws power from nominally OFF devices Ids I e e V V V nv v ds0 1 gs t ds V V V V t t0 ds s sb s EEN
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