EE 434 Lecture 33. Logic Design
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1 EE 434 Lecture 33 Logic Design
2 Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H
3 Review from last time: The two-inverter loop X Y X Y S 2 often eliminated (shorted) S 1 S 1 X Y Y X Standard 6-transistor SRAM Cell
4 Review from last time: Observation V H and V L obtained from the inverter pair transfer characteristics V TRIP can be obtained from either the inverter or the inverter pair transfer characteristics
5 Review from last time: Logic Family Characteristics What properties of an inverter are necessary for it to be useful for building a two-level logic family The inverter-pair transfer characteristics must have three unique intersection points with the V OUT = V IN line What are the logic levels for a given inverter of for a given logic family? The two extreme intersection points of the inverter-pair transfer characteristics with the V OUT = V IN line
6 VIN VOUT
7 (Neglect Case 1 M 1 triode, M 2 cutoff W V L 2 1 OUT I = μ C V V V D1 n OXn IN Tn OUT I = D2 0 1 Equating I D1 and I D2 we obtain: W V L 2 1 OUT 0 = μ C V V V n OXn IN Tn OUT 1 It can be shown that the first solution will not verify, thus V = OUT valid for: 0 V V V < V V GS1 Tn DS1 GS1 Tn thus, valid for: effects) V V V < V V IN Tn OUT IN Tn V V V IN DD Tp V GS2 V Tp
8 (Neglect Case 1 M 1 triode, M 2 cutoff V = OUT 0 effects) V IN V Tn V < V V OUT IN Tn V V V IN DD Tp
9 (Neglect Case 1 M 1 triode, M 2 cutoff V = OUT 0 effects) V IN V Tn V < V V OUT IN Tn V V V IN DD Tp
10 (Neglect effects) Partial solution:
11 (Neglect effects) Case 2 M 1 triode, M 2 sat
12 (Neglect Case 2 M 1 triode, M 2 sat W V L 2 1 μ C p OXp W2 I = V V V 2 L 1 OUT I = μ C V V V D1 n OXn IN Tn OUT Equating I D1 and I D2 we obtain: valid for: V V V < V V V V V V -V GS1 Tn DS1 GS1 Tn GS2 Tp DS2 GS2 T2 thus, valid for: effects) ( ) 2 D2 IN DD Tp 2 μc p OXp W W V 2 ( ) 2 1 OUT V V V μc = V V V 2 L L 2 IN DD Tp n OXn IN Tn OUT 2 1 V V V < V V V V V V -V V-V -V IN Tn OUT IN Tn IN DD Tp OUT DD IN DD Tp
13 (Neglect effects) Case 2 M 1 triode, M 2 sat V -V V-V -V OUT DD IN DD Tp V IN V Tn V < V V OUT IN Tn V V V IN DD Tp
14 (Neglect effects) Case 2 M 1 triode, M 2 sat V -V V-V -V OUT DD IN DD Tp V IN V Tn V < V V OUT IN Tn V V V IN DD Tp
15 Partial solution:
16 (Neglect effects) Case 3 M 1 sat, M 2 sat
17 (Neglect effects) Case 3 M 1 sat, M 2 sat μ C W n OXn 1 I = ( V V ) 2 D1 IN Tn 2 L1 μ C p OXp W2 I = V V V 2 L ( ) 2 D2 IN DD Tp Equating I D1 and I D2 we obtain: 2 μc W μc W 2 L 2 L ( V V V IN DD Tp) = ( V V IN Tn ) 2 2 p OXp 2 n OXn Which can be rewritten as: μc W μc W 2 L 2 L ( V +V V ) = ( V V ) DD Tp IN IN Tn p OXp 2 n OXn 1 V IN 2 1 Which can be simplified to: = μc W μc W 2 L 2 L p OXp ( V ) + ( V +V ) n OXn 1 2 Tn DD Tp This is a vertical line 1 2 μc W μc W + 2 L 2 L n OXn 1 p OXp 2 1 2
18 (Neglect effects) Case 3 M 1 sat, M 2 sat V IN = μc W μc W 2 L 2 L p OXp ( V ) + ( V +V ) n OXn 1 2 Tn DD Tp 1 2 μc W μc W + 2 L 2 L n OXn 1 p OXp Since V IN valid for: C C =C OXn OXp OX = W L this can be simplified to: p ( V ) + ( V +V ) 1 2 Tn DD Tp 1 n 2 W L + μ W μ L 1 p 2 1 n 2 V V V V V GS1 Tn DS1 GS1 Tn thus, valid for: μ W μ L V V V V -V GS2 Tp DS2 GS2 T2 V V V V V V V V V -V V-V -V IN Tn OUT IN Tn IN DD Tp OUT DD IN DD Tp
19 (Neglect effects) Case 3 M 1 sat, M 2 sat V -V V-V -V OUT DD IN DD Tp V IN V Tn V V V OUT IN Tn V V V IN DD Tp
20 (Neglect effects) Partial solution:
21 (Neglect effects) Case 3 M 1 sat, M 2 sat V -V V-V -V OUT DD IN DD Tp V IN V Tn V V V OUT IN Tn V V V IN DD Tp
22 (Neglect effects) Case 4 M 1 sat, M 2 triode
23 (Neglect Case 4 M 1 sat, M 2 triode μ C W n OXn 1 I = ( V V ) 2 D1 IN Tn 2 L1 W2 V -V OUT DD I = μc V V V V -V L 2 Equating I D1 and I D2 valid for: we obtain: V V V V V V V V > V -V GS1 Tn DS1 GS1 Tn GS2 Tp DS2 GS2 T2 thus, valid for: effects) ( ) D2 p OXp IN DD Tp OUT DD 2 μc W W V -V L L 2 2 ( V V ) = μc V V V ( V -V ) n OXn OUT DD IN Tn p OXp IN DD Tp OUT DD 1 2 V V V V V V V V V -V > V-V -V IN Tn OUT IN Tn IN DD Tp OUT DD IN DD Tp
24 (Neglect effects) Case 4 M 1 sat, M 2 triode V -V > V-V -V OUT DD IN DD Tp V IN V Tn V V V OUT IN Tn V V V IN DD Tp
25 (Neglect effects) Case 4 M 1 sat, M 2 triode V -V > V-V -V OUT DD IN DD Tp V IN V Tn V V V OUT IN Tn V V V IN DD Tp
26 (Neglect effects) Partial solution:
27 (Neglect effects) Case 4 M 1 cutoff, M 2 triode
28 (Neglect I = D1 Case 5 M 1 cutoff, M 2 triode 0 W2 V -V OUT DD I = μc V V V V -V L 2 Equating I D1 and I D2 valid for: V GS1 effects) we obtain: ( ) D2 p OXp IN DD Tp OUT DD 2 W2 V -V OUT DD μ C ( ) p OXp V V V V -V 0 IN DD Tp = OUT DD L 2 2 V V V > V -V < VTn GS2 Tp DS2 GS2 T2 thus, valid for: V IN < V Tn V V V V -V > V-V -V IN DD Tp OUT DD IN DD Tp
29 (Neglect effects) Case 5 M 1 cutoff, M 2 triode V -V > V-V -V OUT DD IN DD Tp V IN < V Tn V V V IN DD Tp
30 (Neglect effects) Case 5 M 1 cutoff, M 2 triode V -V > V-V -V OUT DD IN DD Tp V IN < V Tn V V V IN DD Tp
31 (Neglect effects)
32 (Neglect effects)
33 (Neglect effects) From Case 3 analysis: V IN = ( V ) + Tn ( V +V DD Tp ) 1+ μw L μ WL p 2 1 n 1 2 μ W L μ WL p 2 1 n 1 2
34 Inverter Transfer Characteristics of Inverter Pair V IN V OUT
35 Extension of Basic CMOS Inverter to Multiple-Input Gates A B Y Truth Table Performs as a 2-input NOR Gate Can be easily extended to an n-input NOR Gate
36 Extension of Basic CMOS Inverter to Multiple-Input Gates A B Y Truth Table Performs as a 2-input NAND Gate Can be easily extended to an n-input NAND Gate
37 Static CMOS Logic Family M 2 M 2 Pull-up Network PUN V IN V OUT V IN V OUT M 1 M 1 Pull-down Network PDN Observe PUN is p-channel, PDN is n-channel
38 Static CMOS Logic Family M 4 M 3 M 4 A M 3 Y Y A M 1 B M 1 M 2 B M 2 M 2 M 3 M 4 Y V IN V OUT A M 1 M 1 B M 2 n-channel PDN and p-channel PUN
39 General Logic Family p-channel PUN n-channel PDN Arbitrary PUN and PDN
40 Other CMOS Logic Families M 2 M 2 M 2 V OUT V OUT V OUT M 1 V IN V IN M V IN 1 M 1 Enhancement Load NMOS Enhancement Load Pseudo-NMOS Depletion Load NMOS
41 Other CMOS Logic Families M 2 V OUT V IN M 1 Enhancement Load NMOS High and low swings are reduced Response time is slow on LH output transitions Static Power Dissipation Large when V OUT is low Very economical process Termed ratio logic Compact layout (no wells!)
42 Other CMOS Logic Families M 2 M 2 V OUT V OUT A k M 1k V IN M 1 A 1 M 12 Enhancement Load NMOS k-input NOR A 1 M 11 Multiple-input gates require single transistor for each additional input k-input NAND Still useful if many inputs are required (static power does not increase with k
43 Other CMOS Logic Families V OUT M 2 V OUT +V TP V IN M 1 V IN Enhancement Load Pseudo-NMOS High and low swings are reduced Response time is slow on LH output transitions Static Power Dissipation Large when V OUT is low Termed ratio logic
44 Other CMOS Logic Families V OUT M 2 V OUT V IN V IN M 1 Depletion Load NMOS V TD <0 Low swing is reduced Static Power Dissipation Large when V OUT is low Very economical process Termed ratio logic Compact layout (no wells!) Dominant MOS logic until about 1985 Depletion device not available in most processes today
45 Other CMOS Logic Families V OUT -V Tn M 2 V OUT V IN V IN M 1 Enhancement Load NMOS Reduced V H -V L Device sizing critical for even basic operation Shallow slope at V TRIP
46 Other CMOS Logic Families V OUT +V TP M 2 V OUT V IN V IN M 1 Enhancement Load Pseudo-NMOS Reduced V H -V L Device sizing critical for even basic operation Shallow slope at V TRIP
47 Other CMOS Logic Families M 2 V OUT V TD <0 V IN M 1 V OUT Depletion Load NMOS Reduced V H -V L Device sizing critical for even basic operation Shallow slope at V TRIP -V Tp -V Tn V IN
48 Static Power Dissipation in Static CMOS Family M 2 When V OUT is Low, I D1 =0 When V OUT is High, I D2 =0 V IN V OUT Thus, P STATIC =0 M 1 This is a key property of the static CMOS Logic Family and is the major reason Static CMOS Logic is so dominant It can be shown that this zero static power dissipation property can be preserved if the PUN is comprised of n-channel devices, the PDN is comprised of n-channel devices and they are never both driven into the conducting states at the same time
49 Static Power Dissipation in Ratio Logic Families Example: Assume =5V V T =1V, C OX =10-4 A/V 2, W 1 /L 1 =1 and M 2 sized so that V L =V Tn Observe: M 2 V OUT V H = -V Tn If V IN =V H, V OUT =V L so V IN M 1 Enhancement Load NMOS I D1 μc = L OX 1 W 1 V GS1 V T V 2 DS1 V -4 1 ID1 = = 0.25mA 2 P L =(5V)(0.25mA)=1.25mW DS1
50 Static Power Dissipation in Ratio Logic Families Example: Assume =5V V T =1V, C OX =10-4 A/V 2, W 1 /L 1 =1 and M 2 sized so that V L =V Tn M 2 P L =(5V)(0.25mA)=1.25mW V IN M 1 V OUT If a circuit has 100,000 gates and half of them are in the V OUT =V L state, the static power dissipation will be Enhancement Load NMOS
51 Static Power Dissipation in Ratio Logic Families Example: Assume =5V V T =1V, C OX =10-4 A/V 2, W 1 /L 1 =1 and M 2 sized so that V L =V Tn M 2 P L =(5V)(0.25mA)=1.25mW V IN M 1 V OUT If a circuit has 100,000 gates and half of them are in the V OUT =V L state, the static power dissipation will be Enhancement Load NMOS 1 5 P STATIC = mW 2 = 62.5W This power dissipation is way too high and would be even larger in circuits with 100 million or more gates the level of integration common in SoC circuits today
52 Propagation Delay in Static CMOS Family M 2 V IN V OUT M 1 Switch-level model of Static CMOS inverter (neglecting diffusion parasitics)
53 Propagation Delay in Static CMOS Family M 2 V IN V OUT M 1 Switch-level model of Static CMOS inverter (neglecting diffusion parasitics)
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