Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: TwoInput NOR Gate (NOR2)


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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates! Pass Transistor Gates 2 Review: 1st Order RC Delay Models Review: TwoInput NOR Gate (NOR2) τ PHL 0.69 C load R n C load bn + bp + C int + C gb! Equivalent circuits used for MOS transistors " Ideal switch + effective ON resistance + load capacitance " Define unit resistance, R u : effective ON resistance of transistor with min length and W=W u (usually min width) " nmos has effective ON resistance R n = R un /κ n and capacitances κ n, κ n C g " pmos has effective ON resistance R p = R up /κ p and capacitances κ p, κ p C g A (V A ) B (V B ) F (V F ) A (V A ) (A. B) F (V F ) " scale factors κ n 1 and κ p 1, i.e. W n = κ n W un, W p = κ p W up " C gb = C g and b = C sb = for the unit n/pmos transistors " NMOS and pmos transistor at minimum gate length (L) " Capacitance directly proportional to gate width (W) # C = W*C " Conductance directly proportional to gate width (W) # G = W*G " Resistance is inversely proportional to gate width (W) # R = R/W Z (V Z ) B (V B ) (A + B) For Complimentary CMOS: Pullup Net = dual (Pulldown Net) = (A. B) (A + B) 3 4 Review: Elmore Delay: Distributed RC network CMOS NOR2 VTC! The delay from source to node i " N = number of nodes in circuit R ik = τ Di = N k=1 R j C k R ik τ Di = C 1 (R 1 )+ C 2 (R 1 ) +C 3 (R 1 + R 3 ) +C 4 (R 1 + R 3 ) (R j [ path(s 4) path(s k)]) +C i (R 1 + R 3 + R i ) NOTE: τ D = R p C load (0 # 63%) 3 VTC Cases = 0 V; V 2 = 0 V DD = 0 V DD ; V 2 = 0 and V 2 = 0 V DD simultaneously V DD V out simultaneous switching 0 only one input switches V in Switching Threshold Voltage: = V 2 = V out = V th τ p = 0.69τ D (0 # 50%) 5 6 1
2 SwitchRC Transistor Models CMOS NOR2 V th 2input NOR Nets VDD VDD EQV = /2 (W/L) peqv = 1/2 (W/L) p R peqv = 2R p EQV = 2 (W/L) neqv = 2 (W/L) n R neqv = R n /2 7 8 Review: CMOS Inverter: V th CMOS NOR2 V th k ' n! W $ # & ( V in V T 0n ) 2 = k ' p! W $ # & V in V DD V T 0 p 2 " L % 2 " L % n k R ( V th V T 0n ) 2 = V th V DD V T 0 p V T 0n + V th = p ( ) 2 ( ) 2 1 ( V DD +V T 0 p ) k R 1+ 1 k R EQV = /2 EQV = 2 Typically, L n =L p =L min k R = k ' n ( W L) n = µ n ( W L) n = µ nw n k ' p ( W L) p µ p ( W L) p µ p W p 9 10 CMOS NOR2 V th Parasitic Caps for NOR2 (worst case) bn1 = bn2 = EQV = /2 bp1 = bp2 = C sb1p = C sb2p = EQV = 2 Cd Symmetric Inv V th = V DD 2 & EQV EQV =1 =
3 Parasitic Caps for NOR2 (worst case) Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = bn1 = bn2 = bp1 = bp2 = C sb1p = C sb2p = C sb1p = C sb2p = Cd Cd = 0, V 2 = V DD > & V out = 0 > V DD = 0, V 2 = V DD > & V out = 0 > V DD C loadnr C int + R peqv = R p2 +R p1 Lumped Model Parasitic Caps for NOR2 (worst case) Parasitic Caps for NOR2 (worst case) bn1 = bn2 = bp1 = bp2 = bn1 = bn2 = bp1 = bp2 = C sb1p = C sb2p = C sb1p = C sb2p = Cd Cd = 0, V 2 = V DD > & V out = 0 > V DD = 0, V 2 = 0 >V & V out =V DD > 0 C loadnr C int + R peqv = R p2 +R p1 Elmore Model? Parasitic Caps for NOR2 (worst case) SwitchRC Transistor Models bn1 = bn2 = 2input NAND Nets bp1 = bp2 = C sb1p = C sb2p = VDD (W/L) peqv = 2 (W/L) p VDD R peqv = R p /2 Cd (W/L) neqv = 1/2 (W/L) n R neqv = 2R n = 0, V 2 = 0 >V & V out =V DD > 0 Elmore Model?
4 CMOS NAND2 V th CMOS NAND2 V th EQV = 2 EQV = 2 EQV = /2 EQV = / CMOS NAND2 V th Parasitic Caps for NAND2 (worst case) bp1 = bp2 = bp bn1 = bn2 = bn EQV = 2 C sb1n = C sb2n = C sbn = bn EQV = /2 V 2 Symmetric Inv V th = V DD 2 & EQV EQV =1 4 = Parasitic Caps for NAND2 (worst case) Parasitic Caps for NAND2 (worst case) bp1 = bp2 = bp bn1 = bn2 = bn C sb1n = C sb2n = C sbn = bn bp1 = bp2 = bp bn1 = bn2 = bn C sb1n = C sb2n = C sbn = bn V 2 V 2 = V DD, V 2 = V DD > & V out = 0 >V DD
5 Parasitic Caps for NAND2 (worst case) Parasitic Caps for NAND2 (worst case) bp1 = bp2 = bp bn1 = bn2 = bn bp1 = bp2 = bp bn1 = bn2 = bn C sb1n = C sb2n = C sbn = bn C sb1n = C sb2n = C sbn = bn V 2 V 2 =V DD, V 2 = 0 >V & V out =V DD > Previously Ratioed Logic! Restoration and Noise Margins " Allows for gate abstraction! CMOS Gates " Drive outputs railtorail " Only one network turned on in steady state " Only subthreshold leakage current in steady state Today Idea! Ratioed Gates " Break all the rules (nice properties) " No railtorail outputs, steadystatecurrent is not subthreshold " Logic correctness " Performance " Power " Implications! Building both pullup and pulldown can be expensive many gates! Seems wasteful to build logic function twice " Once in pullup, once in pulldown " Large gate capacitance
6 Idea! Maybe only need to build one! Build NFET pulldown " Exploit high N mobility " traditional Ratioed Inverter! Does this work? " What is V out for V in =Gnd? " What is V out for V in =V dd? W P =1 W N = Ratioed Inverter in 22nm Ratioed Inverter in 22nm DC Transfer Function Ratioed Inverter! How do we need to size P to make it work? W N =
7 Ratioed Inverter in 22nm P vs. N! Conclude: still prefer N to P for ratioed logic Noise Margin Tradeoff! What is impact of increasing noise margin? " On size Pass Transistor Logic " On input capacitance 39 Teaser Identify Function! What does this do?! What function is this?
8 ! What is Vout if A=1, B=1?! What is Vout if A=1, B=1? ! What is Vout if A=0, B=1?! What is Vout if A=0, B=1? ! What is Vout if A=0, B=0? if A=1, B=0?! What is Vout if A=0, B=0? if A=1, B=0?
9 Area! Compare PT with CMOS circuit?! Is this a regenerating/restoring gate? Pass TR transfer (B=1)! What does output look like (DC transfer)? " (B=1, notb=0, sweep A, nota=cmos inv(a)) 51 Sweep A 52 CMOS Inverter Transfer Reasonable Input to CMOS Inverter?
10 Pass Transistor xor2 with inv restore Compare CMOS! Is this a fair comparison? Required to use? Restore! What should we add to make substitutable with CMOS? Restore Chain Together! Area? (compare to CMOS)
11 Analyze Stage Delay A=1, B=0, C DB =iff =0? Delay A=1, B=0, iff =0? Delay A=1, B=0, iff =0?! What s the equivalent RC circuit?! What s the equivalent RC circuit? Delay A=1, B=1, iff =0? Delay A=1, B=1, iff =0?! What s the equivalent RC circuit?
12 Delay A=1, B=1, iff =0?! What s the equivalent RC circuit? " What are we ignoring? iff > Contact/Diffusion Capacitance Inverter Delay! C j diffusion depletion! Delay driving another minsized inverter?! C jsw sidewall capacitance! L S length of diffusion " Include iff iff = C j L S W + C jsw ( 2L S +W ) L S W= Delay A=1, B=1, iff 0? (W=1) Delay A=1, B=1, iff 0? (W=1)! What s the equivalent RC circuit?
13 Bonus! What does this do? B A Idea! CMOS Logic " Complimentary dual pullup/down networks! There are other logic disciplines " We have the tools to analyze! Ratioed Logic " Tradeoff noise margin for " Reduced area? Capacitive load? " Dissipates static power in one mode! Can use pass transistors for logic " Sometimes gives area or delay win Midterm Exam Admin! Midterm 3/15! HW 5 due Thursday, 3/3 " In class! Di and Ao OH tonight and tomorrow night 69pm " Starts at exactly 4:30pm, ends at exactly 5:50pm (80 minutes) " Location TBD, posted on Piazza and Course Calendar! Tania OH tomorrow 24pm " Covers Lec 114 (slides 126) " Closed book, no notes or cheat sheets " Calculators allowed " Review Session by TA on Sunday 3/13  time and location TBD! Journal Thursday " Carrizo: A High Performance, Energy Efficient 28 nm APU, pp " Extra office hours on Monday (3/14) and Tuesday (3/15) (time and location TBD)
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