ECE321 Electronics I


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1 ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Slide: 1 CMOS nverter Review of Last Lecture Voltage Transfer Characteristics (VTC) Switching threshold voltage Output high voltage Output low voltage nput high voltage nput low voltage Current Transfer Characteristics (TC) Peak current Slide: 1
2 Today s Lecture Noise Margin Definition Approximation of Noise Margin for CMOS nverter Propagation Delay Rise and Fall Times nput and Self Loading (Load) Capacitances Delay Approximation Slide: 3 Review: Voltage Transfer Characteristics mportant Parameters on VTC: Switching Threshold Voltage V S or V M Gain at V S or V M Output High Voltage V OH Output Low Voltage V OL nput High Voltage V H nput Low Voltage V L Slide: 4
3 Effect of Noise on a CMOS nverter Slide: 5 Noise Margin Noise Margin NM NM H L V V OH L V V H OL t is better to have: V OH = V V OL = V SS Large NM H Large NM L Slide: 6 3
4 Noise Margin in nverter and Buffer VTC of an inverter VTC of a buffer Slide: 7 Example: Noise Margin Calculation Slide: 8 4
5 Noise Margin Approximation How to compute Noise Margin Usually it is harder to compute the exact value of NM Use approximation (gain factor) Determine gain at V M Extrapolate V L and V H V OL and V OH are easy to compute Example: NM L and NM H in CMOS inverter V out V OH V M where 1 g VM V n p Tn V 1 V M V Tp V OL V L V H V in Slide: 9 Example: Noise Margin Approximation A CMOS inverter has V =5V is designed to have V M =.9V. f V Tn =0.7, V Tp =0.5, λ n =0.05 V 1 and λ p =0.08 V 1. Find the noise margins NMH and NML. g V L.9. 77V V H V 16.6 V out V OH NMH V V M NML V V in V OL V L V H Slide: 10 5
6 Dynamic Behavior of CMOS nverter Changing of the input doesn t instantaneously change the out pf an inverter This is mostly due to the time it takes to chrgae or dischage the output/load capacitor t is important to know how long it takes to get the signal out of the inverter or any CMOS logic gate V in V out V in t phl t plh R p, R n V out C in C out Slide: 11 Definition: Propagation Delay Definition of propagation delay is delay from where input crosses 50%Vdd to where output crosses 50%Vdd Remember: the value of 50%Vdd is from switching threshold voltage (V M ) t phl is propagation delay when output switches from High to Low t plh is propagation delay when output switches from Low to High To compute delay, the inverter must be simplified Slide: 1 6
7 Definition: 10%90% Rise/Fall Times Definition of 10%90% rise time is delay from 10%Vdd to 90%Vdd in the output t r is the rise time when output switches from Low to High Definition of 90%10% fall time is delay from 90%Vdd to 10%Vdd in the output t f is the fall time when output switches from High to Low Slide: 13 Definition: Linear Rise/Fall Times Definition of rise time (Hawkin s book) is delay from 0 to Vdd in the output assuming a constant current source model t r is the rise time when output switches from Low to High Definition of fall time (Hawkin s book) is delay from Vdd to 0 in the output assuming a constant current source model t f is the fall time when output switches from High to Low Slide: 14 7
8 Delay Calculation in CMOS nveretr t is not easy to accurately calculate delay in CMOS inverter, because CMOS inverter is a nonlinear circuit, therefore exact delay calculation requires solving a nonlinear differential equation Most of the elements in the circuit is voltage dependent (transistor drive current, parasitic capacitances, channel length modulation, etc.) A simplified model is required for basic calculations and design process Note that SPCE actually does solve the nonlinear circuit accurately, but is only good for final verification, not the design Slide: 15 Gate nput/output Capacitances Components V C GSp C GBp C SBp Miller Caps C GDp C DBp C GDn C GBn C DBn C in C in nput Cap C GSn C SBn C C C C C C GDp GSp GBp GDn GSn GBn C out C out Self Loading Cap GND C C C C GDp DBp GDn DBn Slide: 16 8
9 Propagation Delay Model Q t C V Propagation delay is defined as the time between the input reaching V / and the output reaching V / To simplify the model, let s assume is a constant av V C V t av V out t plh t t 1 CL V av C L Slide: 17 How to compute av? Propagation Delay Model Assume step input NMOS goes into cutoff and stays there PMOS goes into saturation at first because V DS > V GS  V T PMOS will transition to linear, however, before V out reaches V / av DS V 0 V V / out DS out av K p Wp Lp V V V V V tp tp V 8 Slide: 18 9
10 Propagation Delay Model A simpler model for av can be obtained by assuming that the PMOS stays in saturation the whole time, therefore acts as an ideal current source av K p W p L p V V tp t plh CL V t t1 av t plh CL V W p K p L p V V Tp Assuming V >> V Tp t plh CL W p K p V L p Same arguments hold for t phl Slide: 19 Minimum Delay Design Techniques Reduce C in and C out Careful layout, keep drain diffusion area as small as possible Reduce wiring capacitance Careful layout, keep devices as close as possible ncrease (W/L) of devices Need to be careful not to get into selfloading effect ncrease V Need to be careful not to get into V DSAT or velocity saturation Slide: 0 10
11 Example: CMOS nverter Delay A CMOS inverter has V =5V is designed such that (W/L) n =10 and (W/L) p =0. Assume that V Tn =0.7, V Tp =0.6, K n =100 ua/v, K p =60 ua/v, and the load capacitance is 100fF. 1) Use av model to find t phl, t plh, t r(10%90%), and t f(90%10%). ) Use constant current source model to find t phl, t plh, t r(10% 90%), t f(90%10%), t r, and t f. Answers: 1) t phl =9.64 ps, t plh =3.73 ps, t r(10%90%) =56.71 ps, and t f(90%10%) =70.98 ps ) t phl =7.04 ps, t plh =1.5 ps, t r(10%90%) =34.43 ps, and t f(90%10%) =43.7 ps, t r =43.04 ps and t f =54.98 ps. Slide: 1 11
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