EEE 421 VLSI Circuits
|
|
- Chloe Hines
- 3 years ago
- Views:
Transcription
1 EEE 421
2 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in k range) large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors
3 Transforming PMOS I-V Lines Want common coordinate set V in, V out, and I Dn I DSp = -I DSn V GSn = V in ; V GSp = V in - V DSn = V out ; V DSp = V out - I Dn Vout V in = V in = 1.5 V in = V in = 1.5 V GSp = -1 V GSp = -2.5 Mirror around x-axis V in = + V GSp I Dn = -I Dp Horiz. shift over V out = + V DSp
4 CMOS Inverter Load Lines PMOS 2.5 X 1-4 NMOS V in = V V in = 2.5V 2 V in =.5V 1.5 V in = 2.V V in = 1.V V in = 2V.5 V in = 1.5V V in = 2.V V in = 2.5V 1 V in = 1.5V V out (V) V in = 1V V in = 1.5V V in =.5V V in = 1.V V in =.5V V in = V.25um, W/L n = 1.5, W/L p = 4.5, = 2.5V, V Tn =.4V, V Tp = -.4V
5 CMOS Inverter VTC V out (V) NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off V in (V)
6 Operating Regions Revisit transistor operating regions Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out A B C D E V tn /2 +V tp V in
7 Beta Ratio If b p / b n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent V inverter DD V out p.1 n p 1 n V in
8 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range
9 Logic Levels To maximize noise margins, select logic levels at» unity gain point of DC transfer characteristic V out Unity Gain Points Slope = -1 V OH b p /b n > 1 V in V out V OL V tn V IL V IH - V tp V in
10 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes» Requires solving differential equations Input is usually considered to be a step or ramp» From to or vice versa
11 Inverter Step Response Ex: find step response of inverter driving load cap V ( t) u( t t ) V I V in out dv ( t t ) out dt ( t) V I DD dsn C DD ( t) load 2 dsn( t) 2 VDD V Vout VDD Vt Vout ( t) VDD V t V ( t) V V 2 D V out out D t t t V in (t) t I dsn (t) V in (t) V out (t) V out (t) C load t
12 Delay Definitions t pdr : rising propagation delay» Max time from input to rising output crossing /2 t pdf : falling propagation delay» Max time from input to falling output crossing /2 t pd : average propagation delay» t pd = (t pdr + t pdf )/2 t r : rise time» From output crossing.2 to.8 t f : fall time» From output crossing.8 to.2
13 Delay Definitions t cdr : rising contamination delay» Minimum time from input to rising output crossing /2 t cdf : falling contamination delay» Minimum time from input to falling output crossing /2 t cd : average contamination delay» t pd = (t cdr + t cdf )/2
14 Simulated Inverter Delay Solving differential equations by hand too hard SPICE simulator solves equations numerically» Uses more accurate I-V models too! But simulations take time to write (V) V in t pdf = 66ps t pdr = 83ps.5 V out.. 2p 4p 6p 8p 1n t(s)
15 Switching Waveforms Example: = 1. V, C L = 15 ff, f = 1 GHz
Lecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
DC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current
Lecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
Lecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
Lecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
EE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is
5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
DC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling
CMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
THE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
ECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
Digital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :
The CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
MOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
Integrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
EE5311- Digital IC Design
EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM
MOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
Topic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated
4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
CMOS Technology for Computer Architects
CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) 1 2 Recap Threshold Voltage
Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate
EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is
Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance
ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html
CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
VLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter First-Order DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
ECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
The CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the
EE5311- Digital IC Design
EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM
Lecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003
6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
Digital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
MOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (361-1-301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
ECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS
Lecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
COMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic
EE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
Integrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits - 2 guntzel@inf.ufsc.br
CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
Outline. Chapter 2: DC & Transient Response. Introduction to CMOS VLSI. DC Response. Transient Response Delay Estimation
Inroducion o CMOS VLSI Design Chaper : DC & Transien Response David Harris, 004 Updaed by Li Chen, 010 Ouline DC Response Logic Levels and Noise Margins Transien Response Delay Esimaion Slide 1 Aciviy
Properties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
Digital Integrated Circuits 2nd Inverter
Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response
The Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
EECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit
EE115C Digital Electronic Circuits Homework #3
Electrical Engineering Department Spring 1 EE115C Digital Electronic Circuits Homework #3 Due Thursday, April, 6pm @ 56-147E EIV Solution Problem 1 VTC and Inverter Analysis Figure 1a shows a standard
VLSI Design I; A. Milenkovic 1
ourse dministration PE/EE 47, PE 57 VLI esign I L6: omplementary MO Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
Static CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratio-less) static CMOS Covered so far Ratio-ed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003
6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS
EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
CMOS Logic Gates. University of Connecticut 181
CMOS Logic Gates University of Connecticut 181 Basic CMOS Inverter Operation V IN P O N O p-channel enhancementtype MOSFET; V T < 0 n-channel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
Lecture 4: CMOS review & Dynamic Logic
Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent
EE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter
Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)
CMOS Logic Gates. University of Connecticut 172
CMOS Logic Gates University of Connecticut 172 Basic CMOS Inverter Operation V IN P O N O p-channel enhancementtype MOSFET; V T < 0 n-channel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
THE CMOS INVERTER CHAPTER. Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design
chapter5.fm Page 176 Friday, January 18, 2002 9:01 M CHPTER 5 THE CMOS INVERTER Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design 5.1 Introduction
Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS. Kenneth R. Laker, University of Pennsylvania, updated 12Feb15
ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS 1 VDD Vout Vin Ideal VTC Logic 0 = 0 V Logic 1 = VDD 0 2 VOH VDD VOL 0 o.c. Cout For DC steady-state Cout is open circuit. VDD 0 VDD VOL VT0n
COMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
Important! EE141- Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model
- Fall 00 Lecture 5 CMO Inverter MO Transistor Model Important! Lab 3 this week You must show up in one of the lab sessions this week If you don t show up you will be dropped from the class» Unless you
EE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X
Digital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
B.Supmonchai July 5th, q Quantification of Design Metrics of an inverter. q Optimization of an inverter design. B.Supmonchai Why CMOS Inverter?
July 5th, 4 Goals of This Chapter Quantification of Design Metrics of an inverter Static (or Steady-State) Behavior Chapter 5 CMOS Inverter Boonchuay Supmonchai Integrated Design Application Research (IDAR)
VLSI Design I; A. Milenkovic 1
PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe57-3f
VLSI Design I; A. Milenkovic 1
ourse dministration PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka )
Digital Integrated Circuits A Design Perspective
Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In
Power Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #2 EECS141 Due Thursday, September 9, 5pm, box in 240 Cory PROBLEM
Digital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
Chapter 11. Inverter. DC AC, Switching. Layout. Sizing PASS GATES (CHPT 10) Other Inverters. Baker Ch. 11 The Inverter. Introduction to VLSI
Chapter 11 Inverter DC AC, Switching Ring Oscillator Dynamic Power Dissipation Layout LATCHUP Sizing PASS GATES (CHPT 10) Other Inverters Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky;
EE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!
High-to-Low Propagation Delay t PHL
High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to
Circuit A. Circuit B
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 19, 2006 by Karl Skucha (kskucha@eecs) Borivoje Nikolić Homework #9
Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics
Electronic Devices and Circuits Lecture 16 - Digital Circuits: CMOS - Outline Announcements (= I ON V DD
6.01 - Electronic Deices and Circuits Lecture 16 - Digital Circuits: CMOS - Outline Announcements Handout; Web posting - Lecture Outline and Summary; two readings Exam - Wednesday, No. 5, 7:30-9:30 pm,
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic
EECS 141 F01 Lecture 17
EECS 4 F0 Lecture 7 With major inputs/improvements From Mary-Jane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND
Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC
ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics