EECS 141: FALL 05 MIDTERM 1


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1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION First SID Problem 1 (15): 15 Problem (13): 13 Problem 3 (1): 1 Total (4) 4 EECS 141: FALL 5 MIDTERM 1 1
2 PROBLEM 1: VTC, Delay (15 pts) Consider the digital circuit shown in Fig. 1a. Assume shortchannel transistor and you may also assume that all capacitances are constant and linear over the operation range. External load capacitance = 1fF, =.5V, R = 4kΩ. Parameters of NMOS transistor are given below: k = 1 µa/v, V T =.5V, V DSAT =.5V, γ =, λ =, W / L =.5µm /.5µm WL C ox =.6 ff, C DB = C SB =.1 ff, C GD,overlap = C GS,overlap =.1 ff In M D R Fig. 1a I D.5V Diode IV characteristics V D a. Sketch the VTC for this circuit using the diagram below. Clearly indicate break points and operation modes of transistor M and diode D. What is when V in =? (5 pts) (V) V in < V D : D off V in > V D : D on (vel) sat (V in = ) = 1.5V 1.5 off/lin linear V in (V) V in Linear mode: R M V D R < V in <.5V Diode off I D =, (M off/lin) = V in V in =.5V (large bias voltage) assume vel sat W V DSAT V out = VD + R k' ( VDD VT Vout ) VDSAT L = 1.5V (.5pts) Verify assumption: V DS = V in = 1V > V DSAT Also: V GT =.5V = V DSAT edge of sat / vel sat good assumption! (1.5pts) (Vel) sat & λ = constant current until V DS = V DSAT (V in = 1.5V + V DSAT = V) Current: I M = I D = ( V D ) / R = 5µA, = const = 1.5V V DS = V in, V GT = V T linear when V in < V T Equivalent R M (V in = V, = 1.5V): R M = V DS / I M =.5V / 5µA = kω Linear mode: = V D + R / (R + R M ) V in =.5V + /3 V in EECS 141: FALL 5 MIDTERM 1
3 b. Calculate the delay of the circuit in Fig. 1a when the input changes from to. Let V M = 1V and assume that V in was at for a long time before the transition. If you are not sure of your answer in (a), assume that the output reaches final value V high = 1.75V. What are the equivalent capacitance, equivalent resistance, and the delay? (5 pts) Calculation of C eq : C eq = 1.6fF R eq = 13.8kΩ t p = 18.7ps (or 4.3ps) Transistor capacitances are shown in the figure. M C SB C GS CL = M is vel sat at the beginning of transition: C eq,m = C SB + C GS,overlap + /3 WL C ox =.6fF Equivalent capacitance is therefore: C eq = C eq,m + = 1.6fF (3pts) Calculation of R eq : Equivalent circuits at the beginning and midpoint are shown below. In both cases, V min = V DSAT, so M is in velocity saturation. R Vout = R M Vout = V M V D C eq R C eq V Observe: For V GS = V DS = V R NMOS = W V DSAT k' ( V VT ) VDSAT L R calc: V DS = R = 14.3kΩ R eq ( = ) = 14.3kΩ R M calc: V DS = V M R M = kω R eq ( = V M ) = R R M = 13.3kΩ (.5pts) Therefore: R eq = (R eq ( = ) + R eq ( = V M )) / = 13.8kΩ (.5pts) Calculation of delay: Notice that V M is not at 5% of full swing, so we go back to basic principles. τ Starting from V ( t out ( t) = Vhigh 1 e ), we derive propagation delay as follows: Vhigh t p = τ ln t p =.85 R eq C eq = 18.7ps Vhigh VM Using V high = 1.5V from part (a) yields t p = 1.1 R eq C eq = 4.3ps EECS 141: FALL 5 MIDTERM 1 3
4 c. What is the energy dissipated as heat during hightolow transition at the output? Assume input voltage step from to and initial = 1.75V. (1 pt) E diss =.45fJ Energy stored on the output capacitor is dissipated as heat during the discharge operation. Therefore, E diss =.5 C eq V out =.45fJ d. For the circuit in Fig. 1b, determine the final value of V A, V B, V C, assuming initial condition at each of the nodes is 3V and V TP =.5V (ignore body effect). ( pts) 1V V A M A M B V B M C V C V A = 1.5V V B = V Fig. 1b V C = V No current flows into the gate I DA = V A = V GA V TA = 1.5V Since V A < initial V B, M B is also off V B = V A V TB = V Finally, M C passes logic 1 to the output V C = V (.5pts) (.5pts) e. Assuming that switch closes at time t =, what is the output voltage at t = + and t = for the circuit in Fig. 1c? was initially discharged, V TP =.5V. Briefly explain your answer (one line for each point). ( pts) 1V t = V M (t = + ) = 1V 3V Fig. 1c (t = ) = 1.5V t = + : Voltage across cannot change instantaneously stays at 1V t = : No DC current through M is off = V G V TP = 1.5V EECS 141: FALL 5 MIDTERM 1 4
5 PROBLEM : Sizing (13 pts) Assume the inverters are implemented in standard CMOS with symmetrical VTC. Furthermore, assume C intrinsic = C gate (γ = 1). Equivalent resistance and input capacitance of unitsized inverter are R and C, respectively. Sizing factor S 1. a. For inverters in Fig. a, pick the best sizing factors S and S 3 to minimize propagation delay. What is the minimum delay (in terms of t p )? (3 pts) In S = 3 S 3 = 9 S 1 = 1 S =? S 3 =? = 7C Fig. a t p = 1t p Standard buffer problem, size increases geometrically. 3 Optimal fanout is: f = 7 = 3 opt Using wellknown geometric mean result, we get: S = 3, S 3 = 9 All stages have equal delay, so propagation delay is given by: t p = 3t p,stage = 3t p (1 + f opt ) = 1t p b. What is the total energy drawn from supply when the input switches from to? What is the total energy dissipated as heat by the circuit? (Answer in symbolic terms: C, ) ( pts) E supply = 1C The total switched capacitance during 1 at the input is: E diss = 6C C sw = C intrinsic,stage + C gate,stage3 = f C + f C = 1C The total energy taken out of supply (second stage) is: E supply = 1C Energy stored on C sw is E C, 1 =.5C sw V DD = 6CV DD. Energy dissipated as heat is obtained by taking the difference + energy discharged from caps of the first (CV DD ) and third stage (18CV DD ). Therefore, E diss = 6C EECS 141: FALL 5 MIDTERM 1 5
6 c. For inverters in Fig. a (previous page), pick the best sizing S and S 3 to minimize energy consumption. You may assume square wave at the input with period T. What is the total energy consumed for a full cycle ( 1, 1 )? (3 pts) S = 1 S 3 = 1 Energy = min when total C = min. E cycle = 3C S min = 1 S = S 3 = 1. The total capacitance charged during a full cycle ( 1, 1 ) is: C cycle = (C int,stage1 + C gate,stage ) + (C int,stage + C gate,stage3 ) + (C int,stage3 + ) = 3C The total energy consumed for a full cycle is: E cycle = 3C d. What is the delay (in terms of t p ) of the circuit in Fig. b? ( pts) S = 4 In S 1 = 1 = 64C S 3 = 6 Fig. b t p = 18.4t p Parallel inverters can be replaced with equivalent inverter of size S = 1. The delay is simply calculated as: t p = t p (1+1) + t p (1+64/1) t p = 18.4t p EECS 141: FALL 5 MIDTERM 1 6
7 e. Assume you can choose the sizing S and S 4 for inverters in Fig. c. What are the optimal values for minimum delay? What is the delay (expressed in terms of t p )? (3 pts) In S 1 = 1 S =? 4C S 3 = 4 S 4 =? To find the optimal sizing factors for minimum delay, we start from the delay expression. The delay of the circuit in Fig. b, normalized to t p is: d = (1+S ) + (1+8/S ) + (1+S 4 /4) + (1+16/S 4 ) = 16C Fig. c S = S 4 = t p t p = ( ) Taking partial derivative with respect to S and S 4, we get: 8 = S = S = S 8 S 4 4 = Finally, we compute the delay. Observe that the delay of the first two stages is equal (opt fanout = f 1 = ) and the delay of the last two stages is equal (opt fanout = f 34 = ). t p 16 = ( 1 + f1 ) t p t p = 4 ( + ) t p f 34 EECS 141: FALL 5 MIDTERM 1 7
8 PROBLEM 3: General Knowledge (1 pts) a. Determine the region of operation (Off, Linear, Saturation, Velocity saturation) in the following configurations. You may assume that all transistors are shortchannel devices and have identical sizes, =.5V. Assume following transistor parameters: NMOS: V Tn =.4V, k n = 115µA/V, V DSATn =.6V, λ =, γ =.4V 1/, Φ F =.6V PMOS: V Tp =.4V, kp = 3µA/V, V DSATp = 1V, λ =, γ =.4V 1/, Φ F =.6V Explain your reasoning and show your derivations if needed. (5 pts) M 1 V GS1 = V DS1 =.5V V DSAT1 < V GT1 < V DS1 M 1 velocity saturation M V x M 3 V GS3 = < V T3 M 3 off V x = V T M off M 4 V x M 5 V T4 > V T5 (body effect) V DS5 < V GT5 M 5 linear Assume M 4 vel sat and ignore body effect in the first iteration: V x ( V V ) V = ( V V V ) DD T 4 x DD x T 5 V DSAT V DSAT V x =.435V M 4 velocity saturation Note: Body effect will only lower V x and increase V DS4, V GT4 (.435V is the worstcase). EECS 141: FALL 5 MIDTERM 1 8
9 b. The first row of the table given below lists the characteristics of a successful microprocessor designed for desktop systems. A low power version for portable use is desired and several changes are therefore made to the design. Use simple hand calculations to fill in estimates for blank cells in the table. Use the space below to explain your answers (if needed). All transistors exhibit shortchannel IV characteristics. (5 pts) / V T (V) W, L, t ox (relative) C (nf) I SAT (ma) Clock (GHz) Area (mm ) Original.5 / Voltage Scaling 1.5 / General Scaling 1.5 / Power (W) Assuming that voltage scaling factor is U and that transistor dimensions scale with factor S, recall following simple formulas from the general scaling theory: C ~ WL/t ox ~ 1/S I SAT = v sat C ox W (V GT V DSAT ) ~ U f Clk ~ 1/C ~ 1/S Area ~ WL ~ S Power ~ f Clk C ~ U Each entry in the table is worth.5pts (total 4.5pts) +.5pts for formulas/calculations. c. For each of the following statements, indicate whether it is true or false (circle one answer). ( pts,.5 for correct answer,.5 for wrong one) T F (a) The load capacitance of a static CMOS gate has no effect on its VTC. T F (b) The delay of a static CMOS inverter is minimized if (W/L) p / (W/L) n = µ n / µ p. T F (c) Silicided poly lines improve performance by decreasing the capacitance. T F (d) PMOS enters vel. saturation for smaller absolute value of electric field than NMOS. EECS 141: FALL 5 MIDTERM 1 9
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