ECE342 Test 3: Nov 30, :008:00, Closed Book. Name : Solution


 Julius Gilmore
 3 years ago
 Views:
Transcription
1 ECE342 Test 3: Nov 30, :008:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown below. (a) Solve for the DC bias conditions (Specify I E, I C, I B, V E, V C, V B.) Please ignore basewidth modulation (assume V A = ) in determining the DC bias. (b) Redraw the equivalent smallsignal model of the amplifier using the hybridπ model. (Assume midband frequencies.) (c) Specify the values of all smallsignal parameters Solution: (a) (b) I E = 0.1 ma I C = β β + 1 I E =.098 ma I B = I E = 2.44 µa β + 1 V E = (75 Ω)(.1 ma) = 7.5 mv V B = V E = V V C = V B + (100 kω)(2.44 µa) = V (c) = I C V T r π = β =.098 ma = = 3.78 ma/v 25.8 mv 40 = kω A/V r o = V A = 50 V = kω I C.098 ma
2 2. (10 pts) The amplifier of problem 1 is reproduced below (for a changed bias current, and a changed transistor). A smallsignal analysis has been completed to give R in = 263 Ω R out = 87.3 kω A vo = v out v in = 230 RL = Evaluate the voltage gain of the amplifier, v out /v sig. Solution: First use voltage division to get v in (using R in ). Then apply the open circuit gain to get the opencircuit output voltage. Finally, use voltage division to find the output voltage for the applied load. ( ) ( ) v out = (230) = v sig
3 3. (25 pts) The circuit below shows a commonemitter amplifier. You could verify (I hope) that the bias current of the transistor is I C 50 µa. (a) For midband frequencies (where the impedance of both capacitors is negligible), derive the amplifier gain, input resistance R in, and output resistance R out. (b) Derive the transfer function v out (s)/v in (s) in terms of the input capacitor value, and sketch the Bode diagram for the amplifier. (Continue to assume that the emitter capacitor has negligible impedance.) (c) Find the restrictions on the input capacitor C so that the amplifier gain is within 3 db of its midband gain value for all frequencies above 200 Hz. Solution: The equivalent smallsignal model is shown below. I ve included the input capacitance for parts 3b and 3c, although for the first part the capacitor is a short circuit (1/Cs is assumed negligible). = I C 50 µa = V T 25.8 mv = ma/v r π = β = 51.6 kω (a) (shorting the input capacitor) The input resistance and output resistance can be seen by inspection. (For the output resistance, the input source is killed, giving v be = 0. So the controlled current source is off.) R in = 100 kω 170 kω r π = kω R out = 80 kω At midband, v be = v in, giving The amplifier gain is 155 V/V. v out = v be (80 kω) = (80 kω)v in = 155v in (b) To take into account the input capacitor, use voltage division to find the value of v be (c) This gives v be = R in R in + 1/Cs v in = R incs R in Cs + 1 v in R in Cs v out = v be (80 kω) = ( 155) R in Cs + 1 v in v out(s) v in (s) = ( 155) R in Cs R in Cs + 1 The Bode diagram should show the midband gain of 155 (43.8 db), a zero at DC, and a pole at ω 3 db = 1/(R in C) (shown on next page). 1 2πR in C 200 Hz C 1 = 28.1 nf 2πR in (200 Hz)
4
5 4. (20 pts) A PMOS transistor fabricated in a technology for which k p = 300 µa/v 2 and V t = 0.5 V is required to operate with a small v SD as a variable resistor to the +1.8 V supply rail. The resistance must range in value from 100 Ω to 500 Ω. Specify the range required for the control voltage V G (not V GS or V SG ) and the required transistor width W. It is required to use the smallest possible device, as limited by the minimum channel length of this technology (L min =.18 µm) and the maximum allowed voltage of 1.8 V. Solution: The maximum source to gate voltage is 1.8 V, where we re required to have a 100 Ω resistance. 1 (300 µa/v 2 )(W/L)( ) = 100 Ω W L = 1 (300 µa/v 2 )(100 V/A)(1.3 V) = So, select W = 25.64(0.18 µm) = 4.61 µm The resistance will increase as the value of V SG drops. (The resistance is proportional to 1/V ov ). To get 5 times the resistance, drop V ov by a factor of 5, from 1.3 V down to 0.26 V. This corresponds to V SG = = 0.76 V. Since the source is tied to the +1.8 V supply, the gate voltages needed are found by subtracting the values of V SG from +1.8 V. 0 V (for 100 Ω) < V G < 1.04 V (for 500 Ω)
6 5. (20 pts) (a) Complete the design of the circuit below so that M 1 is saturated with I D = 1 ma. Find the restrictions on R 2 so that M 1 remains saturated. k n = 400 µa/v 2 W L = 20 λ = 0 V t = 0.4 V Solution: First, find the required overdrive voltage: I D = 1 ma = k W 2 L V OV 2 = (4 ma/v 2 )VOV 2 V OV = 0.5 V So we need V G = V t = 0.9 V. This determines R 1 = 10 kω For Saturation, we need V D V OV = 0.5 V This gives R kω 1.8 R 2 (1 ma) 0.5 V (b) Complete the design of the circuit below so that Q 1 is forwardactive with I C = 1 ma. Find the restrictions on R 4 so that Q 1 remains forwardactive. Solution: For I C = 1 ma, we ll have V E 9 V, V B 8.3 V, and I B = I C /β = 10 µa. Now solve for the unknown current I: (I + 10 µa)(200 kω) = 8.3 V I = 31.5 µa To get the required 1.7 V drop across R 3, set R 3 = 1.7/(31.5 µa) = kω Finally, select R 4 to make sure that V EC > 0.2 V. The result is R kω (1 ma)r V
7 ECE342 Test 3, Fall 2010 (Last Page) ( i C = αi E = βi B = I s e v BE/V T 1 + v ) CE V A V T = kt q 25.8 mv at T = 300 K α = β β + 1 i D = k W L [ (v GS V t )v DS 1 ] 2 v2 DS i D = k W 2 L (v GS V t ) 2 (1 + λv DS ) λ = 1 = λ V A L k 1 = µ n C ox = k W r DS L (V GS V t ) = k W L V OV [ 2φf V t = V t0 + γ + V SB ] 2φ f = I C r 0 = V A + V CE V A V T I C I C r π = β r e = α
ECE343 Test 2: Mar 21, :008:00, Closed Book. Name : SOLUTION
ECE343 Test 2: Mar 21, 2012 6:008:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationECE343 Test 1: Feb 10, :008:00pm, Closed Book. Name : SOLUTION
ECE343 Test : Feb 0, 00 6:008:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationAssignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.
Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT3 Department of Electrical and Computer Engineering Winter 2012 1. A commonemitter amplifier that can be represented by the following equivalent circuit,
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) OPEN BOOK Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationChapter 13 SmallSignal Modeling and Linear Amplification
Chapter 13 SmallSignal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 131 Chapter Goals Understanding of concepts related to: Transistors
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC baseemitter voltage (note: normally plot vs. base current, so we must return to EbersMoll): I C I S e V BE V th I S e V th
More informationID # NAME. EE255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom
ID # NAME EE255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.
More informationCircle the one best answer for each question. Five points per question.
ID # NAME EE255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions
More informationECE 523/421  Analog Electronics University of New Mexico Solutions Homework 3
ECE 523/42  Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More informationCE/CS Amplifier Response at High Frequencies
.. CE/CS Amplifier Response at High Frequencies INEL 4202  Manuel Toledo August 20, 2012 INEL 4202  Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3
More informationChapter 9 Frequency Response. PART C: High Frequency Response
Chapter 9 Frequency Response PART C: High Frequency Response Discrete Common Source (CS) Amplifier Goal: find high cutoff frequency, f H 2 f H is dependent on internal capacitances V o Load Resistance
More informationHomework Assignment 09
Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationCHAPTER.4: Transistor at low frequencies
CHAPTER.4: Transistor at low frequencies Introduction Amplification in the AC domain BJT transistor modeling The re Transistor Model The Hybrid equivalent Model Introduction There are three models commonly
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationEE105 Fall 2014 Microelectronic Devices and Circuits
EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)
More informationEE 321 Analog Electronics, Fall 2013 Homework #8 solution
EE 321 Analog Electronics, Fall 2013 Homework #8 solution 5.110. The following table summarizes some of the basic attributes of a number of BJTs of different types, operating as amplifiers under various
More informationFinal Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.
Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the opamp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam
More information55:041 Electronic Circuits The University of Iowa Fall Exam 2
Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.
More informationECE 546 Lecture 11 MOS Amplifiers
ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase
More informationECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Openloop Gain: g m r o
More informationGEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of
More informationBipolar junction transistors
Bipolar junction transistors Find parameters of te BJT in CE configuration at BQ 40 µa and CBQ V. nput caracteristic B / µa 40 0 00 80 60 40 0 0 0, 0,5 0,3 0,35 0,4 BE / V Output caracteristics C / ma
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics Lena Peterson 20151013 Outline (1) Why is the CMOS inverter gain not infinite? Largesignal
More information3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti
Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationCommon Drain Stage (Source Follower) Claudio Talarico, Gonzaga University
Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i  v o V DD v bs  v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs  C
More informationECE 255, Frequency Response
ECE 255, Frequency Response 19 April 2018 1 Introduction In this lecture, we address the frequency response of amplifiers. This was touched upon briefly in our previous lecture in Section 7.5 of the textbook.
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Threeterminal device whose voltagecurrent relationship is controlled by a third voltage
More informationEECS 105: FALL 06 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 23:30 Wednesday December 13, 12:303:30pm EECS 105: FALL 06 FINAL NAME Last
More informationEE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)
EE05 Fall 205 Microelectronic Devices and Circuits Frequency Response Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Amplifier Frequency Response: Lower and Upper Cutoff Frequency Midband
More informationECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION  SOLUTIONS (Average score = 78/100) R 2 = R 1 =
ECE 3050A, Spring 2004 Page Problem (20 points This problem must be attempted) The simplified schematic of a feedback amplifier is shown. Assume that all transistors are matched and g m ma/v and r ds.
More informationLecture 04: Single Transistor Ampliers
Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 SingleTransistor
More information55:041 Electronic Circuits The University of Iowa Fall Final Exam
Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a classb amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered
More informationCMOS Analog Circuits
CMOS Analog Circuits L6: Common Source Amplifier1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L  CC A 100
More informationMICROELECTRONIC CIRCUIT DESIGN Second Edition
MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113
More informationAnalog Circuit Design Discrete & Integrated
This document contains the Errata for the textbook Analog Circuit Design Discrete & Integrated The Hardcover Edition (shown below at the left and published by McGrawHill Education) was preceded by a SpiralBound
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX =  4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationMicroelectronic Circuit Design 4th Edition Errata  Updated 4/4/14
Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: 1.35 x 10 6 cm/s Page 58, last exercise,
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationKOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU  Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II )
KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU  Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II ) Most of the content is from the textbook: Electronic devices and circuit theory,
More informationAt point G V = = = = = = RB B B. IN RB f
Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F
More informationCARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130
ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED
More informationBipolar Junction Transistor (BJT)  Introduction
Bipolar Junction Transistor (BJT)  Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS V th " VGS vi  I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationElectronics II. Final Examination
f3fs_elct7.fm  The University of Toledo EECS:3400 Electronics I Section Student Name Electronics II Final Examination Problems Points.. 3 3. 5 Total 40 Was the exam fair? yes no Analog Electronics f3fs_elct7.fm
More informationLecture 28 FieldEffect Transistors
Lecture 8 FieldEffect Transistors FieldEffect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use smallsignal equialent
More information1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)
HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn
More informationCHAPTER.6 :TRANSISTOR FREQUENCY RESPONSE
CHAPTER.6 :TRANSISTOR FREQUENCY RESPONSE To understand Decibels, log scale, general frequency considerations of an amplifier. low frequency analysis  Bode plot low frequency response BJT amplifier Miller
More informationECE342 Test 2 Solutions, Nov 4, :008:00pm, Closed Book (one page of notes allowed)
ECE342 Test 2 Solutions, Nov 4, 2008 6:008:00pm, Closed Book (one page of notes allowed) Please use the following physical constants in your calculations: Boltzmann s Constant: Electron Charge: Free
More information3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an nchannel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3
More informationRefinements to Incremental Transistor Model
Refinements to Incremental Transistor Model This section presents modifications to the incremental models that account for nonideal transistor behavior Incremental output port resistance Incremental changes
More informationDelhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:
Serial : ND_EE_NW_Analog Electronics_05088 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: Email: info@madeeasy.in Ph: 04546 CLASS TEST 089 ELECTCAL ENGNEENG Subject
More informationGEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the
More informationECE 6412, Spring Final Exam Page 1
ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.
More informationI. Frequency Response of Voltage Amplifiers
I. Frequency Response of Voltage Amplifiers A. CommonEmitter Amplifier: V i SUP i OUT R S V BIAS R L v OUT V Operating Point analysis: 0, R s 0, r o >, r oc >, R L > Find V BIAS such that I C
More informationLecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER
Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multistage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier
More informationElectronic Devices and Circuits Lecture 18  Single Transistor Amplifier Stages  Outline Announcements. Notes on Single Transistor Amplifiers
6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,
More informationFrequency Response Prof. Ali M. Niknejad Prof. Rikky Muller
EECS 105 Spring 2017, Module 4 Frequency Response Prof. Ali M. Niknejad Department of EECS Announcements l HW9 due on Friday 2 Review: CD with Current Mirror 3 Review: CD with Current Mirror 4 Review:
More informationLecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen
Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output
More information5. EXPERIMENT 5. JFET NOISE MEASURE MENTS
5. EXPERIMENT 5. JFET NOISE MEASURE MENTS 5.1 Object The objects of this experiment are to measure the spectral density of the noise current output of a JFET, to compare the measured spectral density
More informationErrata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.23, CISW CJSW 88 Line between Eqs. (3.32)
More informationV in (min) and V in (min) = (V OH V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs
ECE 642, Spring 2003  Final Exam Page FINAL EXAMINATION (ALLEN)  SOLUTION (Average Score = 9/20) Problem  (20 points  This problem is required) An openloop comparator has a gain of 0 4, a dominant
More informationDESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OPAMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C
MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OPAMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 Email: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OPAMP It consists of two stages: First
More informationEE214 Early Final Examination: Fall STANFORD UNIVERSITY Department of Electrical Engineering. SAMPLE FINAL EXAMINATION Fall Quarter, 2002
STANFORD UNIVERSITY Department of Electrical Engineering SAMPLE FINAL EXAMINATION Fall Quarter, 2002 EE214 8 December 2002 CLOSED BOOK; Two std. 8.5 x 11 sheets of notes permitted CAUTION: Useful information
More informationChapter 5. BJT AC Analysis
Chapter 5. Outline: The r e transistor model CB, CE & CC AC analysis through r e model commonemitter fixedbias voltagedivider bias emitterbias & emitterfollower commonbase configuration Transistor
More informationP. R. Nelson 1 ECE418  VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418  VLSI Midterm Exam Solutions 1. (8 points) Draw the crosssection view for AA. The crosssection view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationESE319 Introduction to Microelectronics. Output Stages
Output Stages Power amplifier classification Class A amplifier circuits Class A Power conversion efficiency Class B amplifier circuits Class B Power conversion efficiency Class AB amplifier circuits Class
More informationAdvanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 WideSwing Current Mirrors I bias I V I in out out = I in V W L bias 
More informationExact Analysis of a CommonSource MOSFET Amplifier
Exact Analysis of a CommonSource MOSFET Amplifier Consider the commonsource MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel
More informationUniversity of Pennsylvania Department of Electrical and Systems Engineering ESE 319 Microelectronic Circuits. Final Exam 10Dec08 SOLUTIONS
University of Pennsylvania Department of Electrical and Systems Engineering ESE 319 Microelectronic Circuits Final Exam 10Dec08 SOLUTIONS This exam is a closed book exam. Students are allowed to use a
More informationLecture 140 Simple Op Amps (2/11/02) Page 1401
Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationESE319 Introduction to Microelectronics Bode Plot Review High Frequency BJT Model
Bode Plot Review High Frequency BJT Model 1 Logarithmic Frequency Response Plots (Bode Plots) Generic form of frequency response rational polynomial, where we substitute jω for s: H s=k sm a m 1 s m 1
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationLecture 06: Current Mirrors
Lecture 06: Current Mirrors Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture VI 1 / 26 Lowered Resistance Looking into
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationE40M. Op Amps. M. Horowitz, J. Plummer, R. Howe 1
E40M Op Amps M. Horowitz, J. Plummer, R. Howe 1 Reading A&L: Chapter 15, pp. 863866. Reader, Chapter 8 Noninverting Amp http://www.electronicstutorials.ws/opamp/opamp_3.html Inverting Amp http://www.electronicstutorials.ws/opamp/opamp_2.html
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationCHAPTER 7  CD COMPANION
Chapter 7  CD companion 1 CHAPTER 7  CD COMPANION CD7.2 Biasing of SingleStage Amplifiers This companion section to the text contains detailed treatments of biasing circuits for both bipolar and fieldeffect
More informationLecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation
Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 2832; sec 3.2 pp. 128129 Current source Ideal goal Small signal model: Open
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationElectronics II. Midterm II
The University of Toledo f4ms_elct7.fm  Section Electronics II Midterm II Problems Points. 7. 7 3. 6 Total 0 Was the exam fair? yes no The University of Toledo f4ms_elct7.fm  Problem 7 points Given in
More informationPhiladelphia University Faculty of Engineering Communication and Electronics Engineering
Module: Electronics II Module Number: 6503 Philadelphia University Faculty o Engineering Communication and Electronics Engineering Ampliier CircuitsII BJT and FET Frequency Response Characteristics: 
More informationEE 330 Lecture 16. MOS Device Modeling pchannel nchannel comparisons Model consistency and relationships CMOS Process Flow
EE 330 Lecture 16 MOS Device Modeling pchannel nchannel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150
More information6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers
6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology March 8, 2005 Copyright 2005 by Michael H. Perrott Notation for Mean,
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationElectronic Circuits Summary
Electronic Circuits Summary Andreas Biri, DITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationFigure 1: MOSFET symbols.
c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between
More information