The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002


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1 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002
2 Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deepsubmicron effects Future trends
3 The Diode B Al A SiO 2 p n Crosssection of pnjunction in an IC process A p n B Onedimensional representation Al A B diode symbol Mostly occurring as parasitic element in Digital ICs
4 Depletion Region hole diffusion electron diffusion p n (a) Current flow. hole drift electron drift Charge Density  + x Distance (b) Charge density. Electrical Field x (c) Electric field. Potential V W 1 W 2 x (d) Electrostatic potential.
5 Diode Current
6 Forward Bias p n (W 2 ) p n0 L p n p0 pregion W 1 0 W 2 nregion x diffusion Typically avoided in Digital ICs
7 Reverse Bias p n0 n p0 pregion W 1 0 W 2 nregion x diffusion The Dominant Operation Mode
8 Models for Manual Analysis V D + I D = I S (e V D/ T 1) V D + + I D V Don (a) Ideal diode model (b) Firstorder diode model
9 Junction Capacitance
10 Diffusion Capacitance
11 I D (A) Secondary Effects V D (V) Avalanche Breakdown
12 Diode Model R S + V D  I D C D
13 SPICE Parameters
14 What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S R on D
15 The MOS Transistor Polysilicon Aluminum
16 MOS Transistors  Types and Symbols D D G G S NMOS Enhancement D NMOS S Depletion D G G B PMOS S Enhancement S NMOS with Bulk Contact
17 Threshold Voltage: Concept S  V GS + G D n+ n+ nchannel psubstrate Depletion Region B
18 The Threshold Voltage
19 The Body Effect V T (V) V BS (V)
20 I D (A) CurrentVoltage Relations A good ol transistor 4 x 10 6 VGS= 2.5 V 5 4 Resistive Saturation VGS= 2.0 V 3 2 V DS = V GS  V T VGS= 1.5 V Quadratic Relationship 1 VGS= 1.0 V V DS (V)
21 Transistor in Linear S V GS G V DS D I D n + V(x) + n + L x psubstrate B MOS transistor and its bias conditions
22 Transistor in Saturation V GS G V DS > V GS  V T S D n+  V GS  V T + n+ Pinchoff
23 CurrentVoltage Relations LongChannel Device
24 A model for manual analysis
25 I D (A) CurrentVoltage Relations The DeepSubmicron Era 2.5 x Early Saturation VGS= 2.5 V 1.5 VGS= 2.0 V 1 VGS= 1.5 V Linear Relationship 0.5 VGS= 1.0 V V DS (V)
26 u n (m/s) Velocity Saturation u sat = 10 5 Constant velocity Constant mobility (slope = µ) c = 1.5 (V/µm)
27 Perspective I D Longchannel device V GS = V DD Shortchannel device V DSAT V GS  V T V DS
28 I D (A) I D (A) I D versus V GS 6 x x quadratic linear V GS (V) Long Channel 0.5 quadratic V GS (V) Short Channel
29 I D (A) I D (A) I D versus V DS 6 x VGS= 2.5 V Resistive Saturation VGS= 2.0 V x 10 VGS= 2.5 V VGS= 2.0 V 3 2 V DS = V GS  V T VGS= 1.5 V 1 VGS= 1.5 V 1 VGS= 1.0 V 0.5 VGS= 1.0 V V DS (V) Long Channel V DS (V) Short Channel
30 A unified model for manual analysis G S D B
31 I D (A) Simple Model versus SPICE 2.5 x 104 V DS =V DSAT Velocity Saturated Linear V DSAT =V GT V DS =V GT Saturated V DS (V)
32 I D (A) A PMOS Transistor 0 x 104 VGS = 1.0V 0.2 VGS = 1.5V VGS = 2.0V VGS = 2.5V Assume all variables negative! V DS (V)
33 Transistor Model for Manual Analysis
34 The Transistor as a Switch V GS V T S R on I D D V GS = V DD R mid R 0 V DD /2 V DD V DS
35 The Transistor as a Switch
36 The Transistor as a Switch
37 MOS Capacitances Dynamic Behavior
38 Dynamic Behavior of MOS Transistor G C GS C GD S D C SB C GB C DB B
39 The Gate Capacitance Polysilicon gate Source n + x d x d W Drain n + L d Top view Gatebulk overlap t ox Gate oxide n + L n + Cross section
40 Gate Capacitance G G G S C GC C GC C GC D S D S D Cutoff Resistive Saturation Most important regions in digital design: saturation and cutoff
41 Gate Capacitance WLC ox C GC WLC ox C GC 2WLC ox WLC ox 2 C GC B C GCS = C GCD WLC ox 2 C GCS C GCD 3 V GS 0 V DS /(V GS V T ) 1 Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation
42 Gate Capacitance (F) Measuring the Gate Cap I V GS V GS (V)
43 Diffusion Capacitance Channelstop implant N A 1 Side wall W Source N D Bottom x j L S Side wall Substrate N A Channel
44 Junction Capacitance
45 Linearizing the Junction Capacitance Replace nonlinear capacitance by largesignal equivalent linear capacitance which displaces equal charge over voltage swing of interest
46 Capacitances in 0.25 mm CMOS process
47 The SubMicron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic Resistances
48 Threshold Variations V T V T Longchannel threshold Low V DS threshold Threshold as a function of the length (for low V DS ) L V DS Draininduced barrier lowering (for low L)
49 I D (A) SubThreshold Conduction Linear The Slope Factor I D ~ I 0 e qv nkt GS, n 1 C C D ox Quadratic S is DV GS for I D2 /I D1 = Exponential V T V GS (V) Typical values for S: mv/decade
50 SubThreshold I D vs V GS qvgs nkt I D I0e 1 e qv kt DS V DS from 0 to 0.5V
51 SubThreshold I D vs V DS I D I 0 e qv nkt GS 1 e qv kt DS 1 V DS V GS from 0 to 0.3V
52 Summary of MOSFET Operating Regions Strong Inversion V GS > V T Linear (Resistive) V DS < V DSAT Saturated (Constant Current) V DS V DSAT Weak Inversion (SubThreshold) V GS V T Exponential in V GS with linear V DS dependence
53 Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S D W R S R D Drain
54 Latchup
55 Future Perspectives 25 nm FINFET MOS transistor
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