# Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

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1 Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini; Chapter 4, Sections Announcements: 1. Quiz#1: March 14, 7:309:30PM, Walker Memorial; covers Lectures #19; open book; must have calculator No Recitation on Wednesday, March 14: instructors or TA s available in their offices during recitation times Spring 2007 Lecture 10 1

2 Large Signal Model for NMOS Transistor Regimes of operation: ID linear VDSsat=VGSVT saturation I D V DS VGS V GS V BS VGS=VT Cutoff 0 0 cutoff VDS I D = 0 Linear / Triode: I D = W L µ nc ox Saturation Effect of back bias V GS V DS 2 V T V DS I D = I Dsat = W 2L µ nc ox [ V GS V T ] 2 [ 1 λv DS ] V T (V BS ) = V To γ[ 2φ p V BS 2φ ] p Spring 2007 Lecture 10 2

3 Smallsignal device modeling In many applications, we are only interested in the response of the device to a smallsignal applied on top of a bias. I D i d v ds v gs V GS v bs V BS V DS Key Points: Smallsignal is small response of nonlinear components becomes linear Since response is linear, lots of linear circuit techniques such as superposition can be used to determine the circuit response. Notation: i D = I D i d Total = DC Small Signal Spring 2007 Lecture 10 3

4 Mathematically: i D (V GS, V DS, V BS ; v gs, v ds, v bs ) I D ( V GS, V DS,V BS ) i d (v gs, v ds, v bs ) With i d linear on smallsignal drives: Define: i d = g m v gs g o v ds g mb v bs g m transconductance [S] g o output or drain conductance [S] g mb backgate transconductance [S] Approach to computing g m, g o, and g mb. g m i D v GS Q g o i D v DS Q g mb i D v BS Q Q [v GS = V GS, v DS = V DS, v BS = V BS ] Spring 2007 Lecture 10 4

5 Transconductance In saturation regime: i D = W 2L µ nc ox [ v GS V T ] 2 [ 1 λv DS ] Then (neglecting channel length modulation) the transconductance is: g m = i D v GS Q Rewrite in terms of I D : W L µ n C ox( V GS V T) g m = 2 W L µ n C ox I D gm saturation 0 0 ID Spring 2007 Lecture 10 5

6 Transconductance (contd.) Equivalent circuit model representation of g m : G S v gs gm v gs i d D B Spring 2007 Lecture 10 6

7 Output conductance In saturation regime: Then: i D = W 2L µ nc ox [ v GS V T ] 2 [ 1 λv DS ] g o = i D v DS Q = W 2L µ n C ox( V GS V T) 2 λ λi D Output resistance is the inverse of output conductance: Remember also: r o = 1 g o = 1 λi D Hence: λ 1 L r o L Spring 2007 Lecture 10 7

8 Output conductance (contd.) Equivalent circuit model representation of g o : G i d D S v gs r o B Spring 2007 Lecture 10 8

9 Backgate transconductance In saturation regime (neglect channel length modulation): Then: i D W 2L µ nc ox [ v GS V T ] 2 g mb = i D v BS Q = W L µ n C ox( V GS V T) V T v BS Q Since: V T (v BS ) = V To γ[ 2φ p v BS 2φ ] p Then : V T v BS Q = γ 2 2φ p V BS Hence: γ g g mb = m 2 2φ p V BS Spring 2007 Lecture 10 9

10 Backgate transconductance (contd.) Equivalent circuit representation of g mb : G S v gs i d gmb v bs D v bs B Spring 2007 Lecture 10 10

11 Complete MOSFET smallsignal equivalent circuit model for low frequency: G S v gs gm v gs g mb v bs r o i d D v bs B V DS V GS ;; ;; ;; ;;; ;;; ;; metal interconnect to gate n polysilicon gate ; ;;; V BS n source ;; ;;;; y 0 Q N (y) x ptype ;; ;;;; metal interconnect to bulk X d (y) ; n drain ;; ;; Spring 2007 Lecture 10 11

12 2. Highfrequency smallsignal equivalent circuit model Need to add capacitances. In saturation: source ; fringe electric field lines gate ;; drain ; n n C sb q N (v GS ) C depletion overlap L D overlap L db D region C gs channel charge overlap capacitance, C ov C gd overlap capacitance, C ov C sb source junction depletion capacitance (sidewall) C db drain junction depletion capacitance (sidewall) ONLY Channel Charge Capacitance is intrinsic to device operation. All others are parasitic Spring 2007 Lecture 10 12

13 Inversion layer charge in saturation q N (v GS ) = W L Q N (y)dy = W Q N (v C ) dy dv C 0 v GS V T 0 dv C Note that q N is total inversion charge in the channel & v C (y) is the channel voltage. But: Then: dv C dy = i D W µ n Q N (v C ) V GS V T [ ] 2 q N (v GS ) = W 2 µ n Q N (v C ) i D 0 dv C Remember: Q N (v C ) = C ox Then: v GS V T [ v GS v C (y) V ] T [ ] 2 q N (v GS ) = W2 µ n i v GS v C (y) V T D 0 dv C Spring 2007 Lecture 10 13

14 Inversion layer charge in saturation (contd.) Do integral, substitute i D in saturation and get: Gate charge: q N (v GS ) = 2 3 WLC ox( v GS V T) q G (v GS ) = q N (v GS ) Q B,max Intrinsic gatetosource capacitance: C gs, i = dq G dv GS = 2 3 WLC ox Must add overlap capacitance: C gs = 2 3 WLC ox WC ov Gatetodrain capacitance only overlap capacitance: C gd = WC ov Spring 2007 Lecture 10 14

15 Other capacitances NRS = N (source) PS = 2 L diff (source) = W ; NRD = N (drain) PD = 2 L diff (drain) = W ; L diff (source) L L diff (drain) ; AS = W L diff (source) W AD = W L diff (drain) SourcetoBulk capacitance: C sb = WL diff C j 2L diff W ( )C jsw where C j : Bottom Wall at V SB (F / cm 2 ) C jsw : Side Wall at V SB (F / cm) DraintoBulk capacitance: C db = WL diff C j 2L diff W ( )C jsw where C j : Bottom Wall at V DB (F/ cm 2 ) C jsw : Side Wall at V DB (F / cm) GatetoBulk capacitance: C gb small parasitic capacitance in most cases (ignore) Spring 2007 Lecture 10 15

16 What did we learn today? Summary of Key Concepts Highfrequency smallsignal equivalent circuit model of MOSFET G C gd i d D S B v gs Cgs C gb v bs g m v gs g mb v bs r o C sb C db In saturation: g m W L I D r o L I D C gs WLC ox Spring 2007 Lecture 10 16

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