Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007
|
|
|
- Bethany Rogers
- 6 years ago
- Views:
Transcription
1 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order effects (cont.) Reading assignment: del Alamo, Ch. 9, 9.7.3, 9.7.4
2 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-2 Key questions The MOSFET current in the saturation regime is not perfectly saturated. Why? What are the key dependencies of the output conductance? What is the physics of carrier transport in the subthreshold regime? What are the key dependencies of the subthreshold current? Why is the subthreshold current important?
3 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Second-order and non-ideal effects in MOSFET (cont.) Channel length modulation Output characteristics of n-mosfet (2N7000): Note: small but distinct slope in I D V DS characteristics in saturation regime slope increases with V GS
4 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-4 Origin is channel length modulation: To first order, in saturation, V DS no longer controls the electrostatics of the channel I D saturates with further increases in V DS However, increases in V DS beyond V DSsat must be accommodated somehow depletion region opens up at drain-end of channel: G n+ D n+ p inversion layer depletion region l p L y As V DS V DSsat : effective channel length shortens: L L l p lateral field in channel I D : imperfect saturation
5 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-5 Lateral electrostatics in pinch-off region: ρ(y) qn D L-l p L -qn A 0 0 qn(x=0) y ε y (y) ε p ε max 0 0 L-l p L y V(y) V DS V DS -V DSsat V DSsat 0 0 L-l p L y To model Channel Length Modulation, need model for l p vs. V DS.
6 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-6 Main result (see details in notes): l p V DS V DSsat E p where E p is peak field at the pinch-off point: E p q V DSsat kt 2L Note key dependencies: At pinchoff, when V DS = V DSsat, l p = 0 l p linear on V DS V DSsat l p L
7 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-7 Impact on I D Since: I Dsat 1 L Then, channel length modulation implies: l p 1 V DS V DSsat I Dsat = l (1 + ) = (1 + ) L l p L(1 p ) L L L E p L L Assumed that in well designed device l p L Define λ as Channel Length Modulation Parameter (units V 1 ): λ = 1 E p L Then: W I Dsat µ e C ox (V GS V T ) 2 [1 + λ(v DS V DSsat )] 2L λ is a parameter characteristic of the technology
8 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-8 W I Dsat µ e C ox (V GS V T ) 2 [1 + λ(v DS V DSsat )] 2L Features of new term: goes to zero for V DS = V DSsat proportional to I Dsat slope of I D V DS characteristics increases the higher V GS ID VDSsat VGS 0 0 VDS VGS=VT In analogy with BJT, 1/λ sometimes referred to as Early voltage.
9 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-9 Output conductance: slope in I D in saturation regime: I Dsat g o = λi Dsat V DS V GS,V BS Important result: for a given technology, g o only depends on I Dsat : g o I Dsat g o linear V GS impact of channel-length modulation 0 0 saturation cut-off VDS
10 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Output conductance of 2N7000 n-mosfet:
11 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Subthreshold regime Output characteristics of MOSFET in saturation in semilog scale: Transfer characteristics of MOSFET in saturation in semilog scale:
12 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Experimental observations below threshold: I D exponential on V GS I D saturated with V DS down to very small values of V DS q(v GS V T ) I D exp nkt log I D VDS>VDSsat S -1 I off 0 VT VGS subthreshold regime
13 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Two key figures of merit of subthreshold regime: Inverse subthreshold slope, S: voltage required to increase I D by 10X: S = nkt ln10 q If n = 1, S = 60 mv/dec at 300 K. Want S small to shut off MOSFET quickly. In well designed devices, S mv/dec at 300 K. Off current, I off : I off = I D (V GS = 0) For logic CMOS, want I off in na range. I off set by S and V T.
14 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Subtreshold current: MOS structure in weak inversion regime (below threshold). Inversion charge depends exponentially on V GS : with kt q(v V T ) Q e (V ) C sth exp q nkt n = 1 + C sth C ox The subthreshold current shows the dependencies of Q e in weakinversion regime. But, how does this charge flow from source to drain?
15 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture In weak inversion, dominant electrostatic feature is depletion region under gate electron Fermi level in drain, does not grab on electron Fermi level in inversion layer (there is no inversion layer!) Potential distribution under gate set by voltage on gate and not drain: V DS V GS <V T G ID Q e (0) Q e (L) S n+ D V BS =0 n+ weak electron concentration depletion region n+ E C qv DS E c (V DS =0) E fe (V DS =0) p 0 L y V DS E c (V DS ) E fe (V DS ) B In subthreshold regime: no longitudinal field in channel energy band diagram looks like the base of bipolar transistor electrons flow from source to drain by diffusion Diffusion current: dq e I D = WD e dy
16 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture No recombination along channel profile is linear in y: Q e (y = L) Q e (y = 0) I D = WD e L On the source side, V = V GS : kt q(v GS V T ) Q e (y = 0) C sth exp q nkt On the drain side, V = V GD = V GS V DS : All together: kt q(v GS V DS V T ) Q e (y = L) C sth exp q nkt W kt q(v GS V T ) qv DS I D D e C sth exp (1 exp ) L q nkt nkt
17 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture W kt q(v GS V T ) qv DS I D D e C sth exp (1 exp ) L q nkt nkt Notice: V DS = 0 I D = 0. If V DS kt q : W kt q(v GS V T ) I D D e C sth exp L q nkt with: γ n = 1 + = φ f C ox Key dependencies of subthreshold slope: C sth x ox C ox n sharper subthreshold. N A C sth n softer subthreshold. V SB C sth n sharper subthreshold. T softer subthreshold. n reflects electrostatic competition between top gate and body ( bottom gate )
18 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Effect of N A : Figure removed due to copyright restrictions. Yang, Edward S. Microelectronic Devices. New York, NY: McGraw-Hill, 1988, p ISBN:
19 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Effect of V SB : Figure removed due to copyright restrictions. Sze, S. M. Physics of Semiconductor Devices. 2nd ed. New York, NY: Wiley, 1981, p ISBN:
20 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Effect of T: Figure removed due to copyright restrictions. Sze, S. M. Physics of Semiconductor Devices. 2nd ed. New York, NY: Wiley, 1981, p ISBN:
21 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Subthreshold regime important because it determines off current, I off : W kt qv T I off = I D (V GS = 0, V DS = V DD ) D e C sth exp L q nkt To get I off : L performance V T performance n N A short-channel effects x ox field in oxide I off : key goal in logic device design
22 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture I off important because it contributes to DC power dissipation in CMOS: V DD V IN =0 V OUT =V DD I off C L W off = I off V DD Example: I off = 100 pa/µm, W = 5 µm, V DD = 3.3 V W off = 1.7 nw. If 10 7 transistors W off = 17 mw. I off thermally activated: T I off W off. Same example with V th = 0.7 V and S 1 = o C: W off (75 o C) = 74 W off (25 o C) = 1.1 W
23 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture Key conclusions Channel length modulation: as V DS > V DSsat, depletion region widents at drain-end of channel L I Dsat (imperfect saturation). Rough model: W I Dsat µ e C ox (V GS V T ) 2 [1 + λ(v DS V DSsat )] 2L Output conductance due to channel length modulation: g o I Dsat Subthreshold regime: I D drops off exponentially below V T : Inverse subthreshold slope: q(v GS V T ) I D exp nkt C sth kt S = (1 + ) ln 10 q C ox Off current of CMOS, I D (V GS = 0, V DD = 0), set by subthreshold regime. Important for static power dissipation.
Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 28-1 Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007 Contents: 1. Second-order and
MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)
Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture
ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
Lecture 23 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) April 4, 2007
6.720J/3.43J Integrated Microelectronic Devices Spring 2007 Lecture 231 Lecture 23 The Si surface and the MetalOxideSemiconductor Structure (cont.) April 4, 2007 Contents: 1. Ideal MOS structure under
Lecture 22 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) April 2, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 22-1 Lecture 22 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) April 2, 2007 Contents: 1. Ideal MOS structure
6.012 MICROELECTRONIC DEVICES AND CIRCUITS
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6.012 MICROELECTRONIC DEVICES AND CIRCUITS Answers to Exam 2 Spring 2008 Problem 1: Graded by Prof. Fonstad
Lecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
Lecture 30 The Short Metal Oxide Semiconductor Field Effect Transistor. November 15, 2002
6.720J/3.43J Integrated Microelectronic Devices Fall 2002 Lecture 30 1 Lecture 30 The Short Metal Oxide Semiconductor Field Effect Transistor November 15, 2002 Contents: 1. Short channel effects Reading
Microelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
Lecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
ECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
EE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
Device Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
Practice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
MOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 6, 01 MOS Transistor Basics Today MOS Transistor Topology Threshold Operating Regions Resistive Saturation
ECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
EE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
MOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
Lecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
Device Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
Part 4: Heterojunctions - MOS Devices. MOSFET Current Voltage Characteristics
MOS Device Uses: Part 4: Heterojunctions - MOS Devices MOSCAP capacitor: storing charge, charge-coupled device (CCD), etc. MOSFET transistor: switch, current amplifier, dynamic random access memory (DRAM-volatile),
Lecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 17-1 Lecture 17 - The Bipolar Junction Transistor (I) Contents: Forward Active Regime April 10, 2003 1. BJT: structure and basic operation
SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania
1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION
ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University
NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the
Spring Semester 2012 Final Exam
Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters
CMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well
6.01 - Microelectronic Devices and Circuits Lecture 16 - CMOS scaling; The Roadmap - Outline Announcements PS #9 - Will be due next week Friday; no recitation tomorrow. Postings - CMOS scaling (multiple
EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
N Channel MOSFET level 3
N Channel MOSFET level 3 mosn3 NSource NBulk NSource NBulk NSource NBulk NSource (a) (b) (c) (d) NBulk Figure 1: MOSFET Types Form: mosn3: instance name n 1 n n 3 n n 1 is the drain node, n is the gate
6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.
Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
Chapter 13 Small-Signal Modeling and Linear Amplification
Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors
Lecture 11: MOSFET Modeling
Digital Integrated Circuits (83-313) Lecture 11: MOSFET ing Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,
Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -
6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large
Microelectronics Main CMOS design rules & basic circuits
GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September
Lecture #27. The Short Channel Effect (SCE)
Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )
Metal-oxide-semiconductor field effect transistors (2 lectures)
Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -
CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS
CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancement-type N-MOS transistor 5.3 I-V characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
Integrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
ECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.
INEL 6055 - Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ
Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,
The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
Chapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
ECE 305: Fall MOSFET Energy Bands
ECE 305: Fall 2016 MOSFET Energy Bands Professor Peter Bermel Electrical and Computer Engineering Purdue University, West Lafayette, IN USA pbermel@purdue.edu Pierret, Semiconductor Device Fundamentals
MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations
ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 10, Number 2, 2007, 189 197 MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations S. EFTIMIE 1, ALEX. RUSU
ECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
Lecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
Section 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
EE5311- Digital IC Design
EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
MOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically
Section 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
Lecture 35 - Bipolar Junction Transistor (cont.) November 27, Current-voltage characteristics of ideal BJT (cont.)
6.720J/3.43J - Integrated Microelectronic Devices - Fall 2002 Lecture 35-1 Lecture 35 - Bipolar Junction Transistor (cont.) November 27, 2002 Contents: 1. Current-voltage characteristics of ideal BJT (cont.)
EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
The Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
Lecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7
HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2 What do digital IC designers need to know? 5 EE4 EECS4 6 3 0< V GS - V T < V DS Pinch-off 7 For (V GS V T )
FIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
ECE-305: Spring 2016 MOSFET IV
ECE-305: Spring 2016 MOSFET IV Professor Mark Lundstrom Electrical and Computer Engineering Purdue University, West Lafayette, IN USA lundstro@purdue.edu Lundstrom s lecture notes: Lecture 4 4/7/16 outline
MOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
ECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
MOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
MOSFET. Id-Vd curve. I DS Transfer curve V G. Lec. 8. Vd=1V. Saturation region. V Th
MOSFET Id-Vd curve Saturation region I DS Transfer curve Vd=1V V Th V G 1 0 < V GS < V T V GS > V T V Gs >V T & Small V D > 0 I DS WQ inv WC v WC i V V VDS V V G i T G n T L n I D g V D (g conductance
Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)
Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Outline 1. Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime
Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 16-1 Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model April 8, 2003 Contents: 1. I-V characteristics (cont.) 2. Small-signal
EECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "
II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing
II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band
Lecture 6: 2D FET Electrostatics
Lecture 6: 2D FET Electrostatics 2016-02-01 Lecture 6, High Speed Devices 2014 1 Lecture 6: III-V FET DC I - MESFETs Reading Guide: Liu: 323-337 (he mainly focuses on the single heterostructure FET) Jena:
! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS
Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2
ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling
ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered
ECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2
Long Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:
Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure
Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with
6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
Introduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
DC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling
Technische Universität Graz. Institute of Solid State Physics. 11. MOSFETs
Technische Universität Graz Institute of Solid State Physics 11. MOSFETs Dec. 12, 2018 Gradual channel approximation accumulation depletion inversion http://lampx.tugraz.at/~hadley/psd/l10/gradualchannelapprox.php
nmosfet Schematic Four structural masks: Field, Gate, Contact, Metal. Reverse doping polarities for pmosfet in N-well.
nmosfet Schematic Four structural masks: Field, Gate, Contact, Metal. Reverse doping polarities for pmosfet in N-well. nmosfet Schematic 0 y L n + source n + drain depletion region polysilicon gate x z
ECE315 / ECE515 Lecture-2 Date:
Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode
MOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
EE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM: