ECEN474/704: (Analog) VLSI Circuit Design Spring 2018


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1 ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & MixedSignal Center exas A&M University
2 Announcements If you haven t already, turn in your 0.18um NDA form ASAP ab 1 starts Jan 31 Current Reading Razavi Chapters 2 & 17 2
3 Agenda MOS ransistor Modeling Physical Structure hreshold oltage, DC I Equations Body Effect Subthreshold Region 3
4 NMOS Physical Structure n+ n+ [Karsilayan] 4
5 CMOS Physical Structure [Karsilayan] 5
6 hreshold oltage, [Razavi] Applying a positive voltage to the gate repels holes in the psubstrate under the gate, leaving negative ions (depletion region) to mirror the gate charge Before a channel forms, the device acts as 2 series caps from the oxide cap and the depletion cap If G is increased to a sufficient value the area below the gate is inverted and electrons flow from source to drain 6
7 Definition C Q [Silva] MS dep ox MS 2 Q C dep ox is the ermi potential, is the gate cap/area, C N ox sub MS is the depletion region charge, Q t ox ox 2 dep k Nsub ln q n i is substrate doping density, 2 is the difference between the work functions of 4q si he threshold voltage,, is the voltage at which an inversion layer is formed the polysilicon gate and the silicon substrate or an NMOS this is when the concentration of electrons equals the concentration of holes in the p  substrate N sub n i is undoped silicon electron density Note, will be defined later 7
8 MOSE in Accumulation Mode [Silva] If a negative gate voltage is applied w.r.t. the source, then positive charge accumulates below the gate In this Accumulation Mode, no current flows and the device is often used as a capacitor with the drain shorted to the source his capacitor consists of parallel plate capacitance below the gate and overlap/fringing capacitance near the drain/source regions C 2C G, acc eff Cox ov 8
9 MOSE in Inversion Mode Subthreshold 0< G < >0 Ntype transistor I inear region [Silva] 3 Saturation 2 Subthreshold riode/inear G > Small Saturation G > >  1 Subthreshold (extremely lowvoltage lowpower applications) inear region (voltage controlled resistor, linear OA s, multipliers, switches) Saturation region (Amplifiers) 9
10 MOS Equations in riode Region (Small ) [Sedra/Smith] I I Capacitance per unit gate area : C ox t ox ox Current from Source to Drain : Incremental Charge Density : Gate  to  Channel oltage: I I C I dx n OX C n C n OX OX GC ( d x C n 1 2 OX CS OX GC CS x dv Electron elocity : nex n dx dv I I COX ( CS ( x) ) n dx 0 0 Q dq I dt ( x) C dq dx dx dt ( ( x)) dv Q d x x x ( x) ( x) ) Electron mobility : n 10
11 riode or inear Region [Silva] x x=0 x= Channel depth and transistor current is a function of the overdrive voltage, , and Because is small, GC is roughly constant across channel length and channel depth is roughly uniform I n C OX n 0. 5 GC 0 0 x x x or small x R (x) = Channel Source oltage C ox 1 n 11
12 MOS Equations in riode Region (arge ) Drain current: Expression used in SPICE level 1 GND tox I n C OX n 0. 5 N+ N+ GND I Dsat I D inear approximation his doesn t really happen tox N+ N+ > Nonlinear channel sat sat n
13 riode Region Channel Profile Recall that the channel charge density is ( GC (x)  ) GC x x O x ChannelSource oltage, (x) [Sedra/Smith] If GC is always above throughout the channel length, the transistor current obeys the triode region current equation 13
14 Saturation Region Channel Profile Channel oltage, (x) GC x x O x hen  = O, GC no longer exceeds, resulting in the channel pinching off and the current saturating to a value that is no longer a function of (ideally) [Sedra/Smith] 14
15 Saturation Region [Silva] sat =   sat GC x x x x=0 x= x 0 0 x Channel pinchesoff when =  and the current saturates After channel charge goes to 0, the high lateral field sweeps the carriers to the drain and drops the extra voltage I C n I OX nc 2 OX n 2 2 n n sat n 15
16 NMOS I D Characteristics O N [Sedra/Smith] I n OX n 5 C 0. I C 2 2 n OX n 16
17 MOS argesignal Output Characteristic [Sedra/Smith] Note : O and k ' n C n ox 17
18 hat about the PMOS device? NMOS PMOS [Silva] he current equations for the PMOS device are the same as the NMOS EXCEP you swap the current direction and all the voltage polarities NMOS inear: I n C OX n 0. 5 Saturation: I ncox n 2 PMOS I C 0. 5 I SD pcox SG p 2 SD p OX SG p SD SD
19 PMOS I D SD Characteristics O SG P [Karsilayan] (Saturation) 19
20 Body Effect [Razavi] If the body and source potential are equal, a certain G = 0 is required to form an inversion layer Q 2 dep0 0 MS 2 MS 2 Cox As S becomes positive w.r.t. B, a larger depletion region forms, which requires a higher G to form a channel 0 2 Body effect coefficient, 2 typically ranges from 0.3 to 0.4 SB 2q N C si ox sub 1 2 he net result is that increases due to this body effect Note, it also works in reverse, as if you increase B w.r.t. S, then lowers 20
21 AMU J. SilvaMartinez Drain current, riode region MOS MODE: SPICE EEII NMOS: PMOS: I n C OX n 0. 5 I SD p C OX SG p 0. 5 SD SD Drain Current, Saturation region hreshold voltage (zero bias) NMOS: PMOS: I I SD nc 2 pc 2 OX OX 0 MS 2 2 n 2 SG 2 p hreshold voltage 2 SB SB KP and (Spice Model) KP C OX ; 2q N C si OX sub 21
22 Subthreshold Region So far we have assumed that I D =0 when < However, in reality an exponentially decreasing current exists for < In subthreshold region : I D I 0 q exp k where I 0 is a scale current 1is a nonideality factor he steepest subthreshold slope is1dec./60m with 1 [Razavi] values are often set by extrapolating above threshold data to current values of zero or infinite R on A rough value often used is the which yields I D /=1A/m 22
23 Subthreshold Current & Scaling his subthreshold current prevents lowering excessively Assuming =300m and has an 80m subthreshold slope, then the I on /I off ratio is only on the order of 10^(300/80)=5.6e3 Reducing to 200m drops the I on /I off ratio to near 316 If we have a large number of off transistors on our chip these subthreshold currents add up quickly, resulting in significant power dissipation his is a huge barrier in CMOS technology scaling and one of the main reasons dd scaling has slowed 23
24 Next ime MOS ransistor Modeling SmallSignal Model Spice Models 24
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