MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA


 Allen Allen
 4 years ago
 Views:
Transcription
1 MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA
2 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing a threeelectrode amplifying device based on the semiconducting properties of copper sulfide. He did not demonstrate the device experimentally 2
3 MOS Transistor Demonstrated! Dawon Kahng John Atalla John Atalla and Dawon Kahng at Bell demonstrate the first successful MOS fieldeffect amplifier. 3
4 Outline Currentvoltage characteristics! Scaling and short channel behavior! Future MOS technologies! 4
5 MOS Transistor! The theory developed for the MOS capacitor can be extended directly to the MOS FieldEffectTransistor (MOSFET) by considering the following structure.! V g 0 y L n + source n + drain depletion region polysilicon gate x z ptype substrate Vbs gate oxide inversion channel V ds Enhancement mode MOSFET W V G provides control of surface carrier densities: Q=CV! For V G << V T, the structure consists of two diodes back to back and only leakage currents flow.! When V G is only slightly below V T a depletion region will be formed.! For V G > V T, an inversion layer, i.e., a conducting channel, exists between source and drain and current will flow.! For any further increase in V G the excess potential will result in an increase in the electron density in the channel! 5
6 NMOS Transistor 3D Band Diagram! Nchannel enhancement mode MOSFET, V T > 0! Pchannel enhancement mode MOSFET, V T < 0! V G = V D = 0 no carriers in the channel! electron current V G > 0, V D = 0 carriers in the channel but no movement between source and drain! V G > V T,, V D > 0 electrons flow from source to drain! Source: Sze (1981) 6
7 Variation of Drain Current with V D! (a) N+ Inversion Layer V (+) P G Depletion Region N+ +V D (small) Ι D I D Linear region! I D α V D! V D (b) N+ P V (+) G N+ +V D Ι D I D Before pinch off! V D (c) N+ Inversion layer pinches off V V D = V G D SAT ID N+ P Inversion layer pinch off! Onset of saturation! V D (d) N+ N+ Inversion layer ends V V D > V G D SAT I D P V D Saturation region I D constant with V D. (Assumption valid only for long channel)! 7
8 Complementary MOS (CMOS) Technology Nchannel MOSFET V g > 0 Pchannel MOSFET V g < 0 < 0 All the polarities for Pchannel MOSFET are opposite to that of Nchannel MOSFET 8
9 Currentvoltage characteristics! Increase in V G will result in an increase in the electron density in the channel and thus the drain current.! After pinch off drain current saturates.! Nchannel MOSFET Pchannel MOSFET I DS V DS V GS V G < V T! V GS V DS I DS For Pchannel MOSFET, all of the polarities are reversed and the inversion layer exists for V G < V T! 9
10 CMOS Inverter! V DD V DD PMOS R p V in V out V out V out NMOS R n V in = V DD V in = 0 For V g < V t the transistor is off represented by open circuit! For V g > V t the transistor is on represented by a resistor! Output is an inverted form of input waveform! CMOS inverter is the most important building block of modern logic circuits! What is the power dissipation in this circuit?! 10
11 Gradual Channel Approximation! Linear Region (small V D )! Beyond Pinchoff! p y Vertical field E x inversion layer charge! Lateral field E y flow of carriers from source to drain! Ex ρ ( x) = x ε si C ox V g = (Q i + Q d ) Q i = C ox ( Vg Vt ) inversion depletion 11 E x x E + y y = ρ ( x, y) ε E E x y >> x y Qi ( y) Cox ( Vg V ( y) Vt ) si
12 Current Voltage Dependence! dn(y) J e (y) = qd n dy Diffusion! + qµ n n(y)ε y Drift! Charge/Area! Q i (y) = qn s (y) C ox (V g V(y) V t ) y dq ( y) dy n s J J e e dv ( y dy i ) Cox 0 ( y) = n( x, y) dx & = q$ D % = D n n d ( Q ( y) / q) i dy & dqi ( y) # $! + µ nq % dy " i Sheet Charge density!, dv ( y) )# ( Q ( y) / q) * '! " + µ Current / Width (zdirection)! n i + dy ( & dv ( y) # ( y) $! % dy " 12 (1)!
13 Current vs Voltage! J e = D n & dqi ( y) # $! + µ nq % dy " i & dv ( y) # ( y) $! % dy " Diffusion! Drift! y Note that E y and Q i (y) are negative! When V GS >V T & V DS >V T diffusion current is negligible!! J J e L e 0 = µ Q ( y) n dy = µ C i n ox dv ( y) dy V DS 0 ( V GS V V t ) dv J D = W L µ # nc ox (V GS V t )V DS 1 2 V 2 DS $ % Qi ( y) Cox ( Vg V ( y) Vt ) & ( (2)! ' 13
14 For the case where backside is grounded (V B = 0) V T is given by the equation,! Threshold Voltage! V T = V FB + t ox 2ε ε s qn ( a 2 φ ) p 2φ p ox (3)! In many circuit applications backside is biased. For finite value of V B! V G = V FB + V ox + φ s  φ p + V B N+ V G N+ D P V B 14
15 Effect of Back Bias! V B = 0 V B < 0 15
16 Effect of Back Bias! In a normal MOS capacitor, application of V B will result mostly in change in V ox as φ s is fixed at φ p. If there is a nearby ntype region (drain) which contacts with the inverted surface layer the situation changes. When the surface is inverted, there is basically a PN junction at the surface. A reverse bias can be applied across the PN junction. If V B is zero, inversion occurs when φ s = φ p. If V B < 0, the semiconductor still attempts to invert when φ s reaches φ p. However, with V B < 0 any inversionlayer carriers that do appear at the semiconductor surface migrate laterally into the source and drain because these regions are at a lower potential. Not until φ s = φ p  V B, will the surface invert and normal transistor action begin. In essence, back biasing changes the inversion point in the semiconductor from φ p to φ p  V B. 16
17 Effect of Back Bias! An applied reverse bias between the induced surface nregion and the bulk increases the charge Q d in the depletion region. Since the negative charge induced by V G  V B is shared between the depletion and inversion layers, an increase of the charge in the depletion layer means that there is less charge available to form the inversion layer for a given gate voltage. Looked at another way, more gate voltage must be applied to induce the same number of electrons in the inversion layer when there is a reverse bias. With reverse bias present, the surface potential at the onset of strong inversion becomes φ s = φ p + (V D  V B ) rather than φ s = φ p. 17
18 With V D and V B applied: x dmax = 2κ sε o ( 2φ p +V D V B ) qn a V T = V D + V FB + t ox 2 K s ε o qn ( a V D 2φ p V ) B 2φ (4) p ε ox where ' C ox = ε ox t ox A = C ox A 18
19 For small values of V D and V B = 0, Expression for I D can be approximated by!!!!!!!!!!!!! This is known as LINEAR REGION.! These equations are valid only as long as an inversion layer exists all the way from source to drain (LINEAR REGION).! As V D, the effective voltage between the gate and the channel near the drain will become less than V T. This happens when V G  V T = V D. This value of drain voltage is called the saturation voltage V DSAT (or pinch off voltage because the channel is pinched off at the drain), and for higher drain voltages, a channel will not exist all the way to the drain.! I D = W L µ n ε ox t ox $ (V GS V t )V DS 1 2 V 2 DS % & N+ Inversion layer ends (pinches off) V V D > V G P ' ( ) W L µ ε ox n (V GS V t )V DS t ox N+ D SAT Depletion Region (5) 19
20 V V D > V G D SAT N+ Inversion layer ends (pinches off) P N+ Depletion Region Electrons drift along in the inversion layer and are injected into the depletion region. There the high electric field pulls them into the drain.! Further increase in V D does not change I D (to first order), I D is constant for V D > V DSAT (SATURATION REGION).! Exact V DSAT can be derived by letting Q I (y=l) = 0 in equation!! Q Q ( L) C ( V V, V ) = 0 i i ( y) Cox ( Vg V ( y) Vt ) ox g!!!!!!! V = ( V!! D, Sat! g! t!!!(6)! D V Sat ) 20 t!
21 If (6) is substituted into (5), the saturation current is!!!!!!!!!(7)! I DSAT W 2L µ n ε ox ( ) 2 t ox V G V T Further increase in V D does not change I D (to first order), I D constant for V D > V DSAT! SATURATION REGION.! 21
22 Why does the current remain constant past pinchoff (saturation): 5V V G> V T S N+ N+ D P Depleted Why doesn t increasing V D also increase I? If the current is constant, then the electric field, Ε, must also be constant along most of the channel. 22
23 Why the current remains constant past pinchoff (saturation):! 5V V G> V T S Voltage N+ N+ P Depleted D Near pinchoff, the voltage is decreasing approximately linearly, hence the Ε field is relatively constant throughout.! 23
24 Why the current remains constant past pinchoff (saturation):! 10V V G> V T S Voltage N+ N+ P Depleted D At higher V d, there is a larger depleted region, hence, greater voltage drop.! Ε is still linear in the channel but very large in depletion region.! Carriers rapidly get swept out of depletion region! 24
25 Exact Expressions! V T ( y) = V FB + 1 C ox! [ ( ( ))] 2φ p + V( y) 2ε s qn a 2φ p V B V y Q I ( y) = " [ ( )] + 2ε s qn a 2 φ p V B + V( y) C ox V G V FB + 2φ p V y [ ] I D = W L µ + % n C ox " V G V FB + 2φ p V ( D, & ' 2 ) * V D 23 2qε N % s a ' V D 2 φ p V B & ( ) 3 2 ( 2φ p V B ) 3 2 (/ * 0 ) 1 V DSAT = V G V FB + 2φ p + q ε s N a % & ( % 2 C ox '( ( ) q ε s N a C 2 ox V G V FB V B ) + * + 25
26 What about the Diffusion Current?! V GS =0 V DS =0! E c! J e = D n & dqi ( y) # $! + % dy " µ Q n i & dv ( y) # ( y) $! % dy " E f! Diffusion! Drift! E c! E fn! E v! E v! V GS ~0 V DS =+V DD! V DD! Subthreshold regime Most of the V DS drops across the reversebiased SD Junction. The Channel bands are still ~ flat. Therefore J drift is negligible Gradient of free carriers along channel is large. Diffusion component J diffusion dominates. 26
27 Subthreshold Behavior! I D Log[I D ] Fermi Dirac distribution channel Subthreshold current Ideal source V T V GS V GS V G When the surface is in weak inversion (i.e., 0 < φ s < φ p, V G < V T ), a conducting channel starts to form and a low level of current flows between source and drain.! Diffusion current due to carriers from source spilling over source barrier into channel due to application of V G to lower φ s! Weak dependence on V DS in longchannel FET! drain 27
28 I OFF Log[I D ] V T Subthreshold Conduction! $ I ON Q e (y) exp φ ' s Inversion charge & ) % kt /q( Subthreshold swing S is limited to mkt/q V G φ S = where Drain current C ox C ox + C S ( ( ) = V G V T ) V G V T m m = C + C ox S C ox $ I D Q e exp V G V T ' & ) % mkt /q( V G! φ s C ox C s = Channel Capacitance S = Subthreshold swing V G (logi D ) = V G φ S Gate to channel potential coupling m > 1 in MOSFET φ S (logi D ) = $ 1+ C S & % C ox ' ) kt ( q 60 mv/dec due to FermiDirac distribution 28
29 V T Extraction " I DSAT W 2 L µ n = W 2 L µ n V D = V G!! ε ox ( V G V T ) 2 t ox ε ox ( V D V T ) 2 t ox The intercept of I D vs V D gives the value of threshold voltage V T. This technique is widely used to extract the value of V T.! The region depicted by the dotted curve below V T is the WEAK INVERSION REGION.! 29
30 Effect of Substrate (Back Gate) Bias! For small V D N+ V P G V B N+ The change in V T due to V B is described as! D [ ]! ΔV! T = 1! 2ε C # s qn! a! 2φ p V! B! 2φ p!!(8)! ox!!!!!!!!!! 1 2ε C ox # s qn a V B = γ V B V T = V FB + t ox 2 K s ε o qn ( a 2φ p V ) B 2φ p ε ox 30 The body voltage (or backside bias) makes it easier or harder to reach inversion: > Change in threshold voltage (V T ). (9)!
31 Where!! γ = 1 2ε!! C #! s qn! a = body factor (10) ox!!!!! Equations (5) and (7) can be used to approximate the IV characteristic if V T is replaced with V T + V T.! 31
32 Channel Length Modulation! V G V D > V D SAT N+ V D 2 V D1 N+ P In the saturation region, as V D é, the depletion region near drain expands, the pinchoff point of the channel moves back towards source. The effective channel becomes shorter, I D é because it is proportional to µ/l eff. The depletion region expands as V D assuming a step junction. Provided the device has a channel length >> ΔX D then the change in channel length is approximated by difference in the depletion width of a step junction. Δ L 2 ε s q N a V D V DSAT ( ) (11) 32
33 The decrease in L is responsible for an increase in I D in the saturation region.!! Ι D Therefore, a finite output impedance results. For most applications, this is modeled as! ( ) 2 ( 1+ λv D )! I DSAT =! W!!!!!!!! 2L µ n C ox " V G V T (12) where λ = channel length modulation parameter! V D 33
34 Circuit Models! The MOS transistor may be modeled in the following manner, by inspection of its physical structure. V V V 34
35 Of the elements in the model, only the gate to channel capacitance is essential; the rest are parasitic elements which degrade performance. Technology improvements are generally designed to reduce these parasitics. In many cases, the equivalent circuit can be reduced to the following for small signals: G C GD D C GS g V m G r ds C DB S Note that many of the parameters in the model are voltage sensitive. Accurate large signal model usually requires computer techniques. 35
36 Transconductance, g m! Defined from the I D V D characteristics in both the linear and saturation regions I D = W L µ ε ox n [ V t G V T ]V D ox I DSAT W 2 L µ n ε ox ( V t G V T ) 2 ox The transconductance or gain of the device is defined as: g m = I D V G V D = const 36
37 g m = I D V G V D = const W L µ n ε ox t ox V D W L µ n ε ox t ox for V D < V DSAT, linear region ( V G V T ) for V D >V DSAT, saturation region (13) B. Gate Capacitances, C GS and C GD The gate capacitances vary as the device moves from the linear to saturation region, C GS = 1/2 C ox to 2/3 C ox from linear to saturation (14) C GD = 1/2 C ox to 1/3 C ox from linear to saturation (15) 37
38 Output Impedance, r ds! The output impedance or resistance of the device is defined as: r ds = V D I D & W ( L µ n ' V G = const ε ox t ox 1 ( ) V G V T ) + * for V D < V DSAT, linear region 1 λi D for V D > V DSAT, saturation region (16) Note: Small signal model applicable to analog applications is NOT APPLICABLE to digital applications. 38
MOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationLecture 29  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 20, 2007
6.720J/3.43J  Integrated Microelectronic Devices  Spring 2007 Lecture 291 Lecture 29  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 20, 2007 Contents: 1. Nonideal and secondorder
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationEE105  Fall 2005 Microelectronic Devices and Circuits
EE105  Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Crosssection and layout
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ualwell TrenchIsolated
More informationFIELDEFFECT TRANSISTORS
FIELEFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancementtype NMOS transistor 3 IV characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationLecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)
Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationLong Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to MetalOxideSemiconductor FieldEffect transistors (MOSFET) by considering the following structure:
More informationECE315 / ECE515 Lecture2 Date:
Lecture2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS IV Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cutoff Linear/Triode
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic nchannel MOSFET (Figure 1) consists of two heavilydoped ntype regions, the Source and Drain, that comprise the main terminals of the device. The
More informationLecture #27. The Short Channel Effect (SCE)
Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! medamine.miled@polymtl.ca!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationChapter 2 CMOS Transistor Theory. JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor JinFu Li, EE,
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationThe Gradual Channel Approximation for the MOSFET:
6.01  Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v
More informationECE305: Fall 2017 MOS Capacitors and Transistors
ECE305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525530, 563599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationChapter 13 SmallSignal Modeling and Linear Amplification
Chapter 13 SmallSignal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 131 Chapter Goals Understanding of concepts related to: Transistors
More informationFundamentals of the Metal Oxide Semiconductor FieldEffect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor FieldEffect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationCHAPTER 5 MOS FIELDEFFECT TRANSISTORS
CHAPTER 5 MOS FIELDEFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancementtype NMOS transistor 5.3 IV characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5
More informationMetaloxidesemiconductor field effect transistors (2 lectures)
Metalidesemiconductor field effect transistors ( lectures) MOS physics (brief in book) Currentvoltage characteristics  pinchoff / channel length modulation  weak inversion  velocity saturation 
More informationMOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor
MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More information6.012 MICROELECTRONIC DEVICES AND CIRCUITS
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6.012 MICROELECTRONIC DEVICES AND CIRCUITS Answers to Exam 2 Spring 2008 Problem 1: Graded by Prof. Fonstad
More informationLECTURE 3 MOSFETS II. MOS SCALING What is Scaling?
LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and
More informationLecture 28  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 18, 2007
6.720J/3.43J  Integrated Microelectronic Devices  Spring 2007 Lecture 281 Lecture 28  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 18, 2007 Contents: 1. Secondorder and
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationMicroelectronics Main CMOS design rules & basic circuits
GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationCHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS
98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 1  The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More informationNanoscale CMOS Design Issues
Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI1 Class Transistor IV Review Agenda Nonideal
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ FieldOxyde (SiO 2 ) psubstrate p+ stopper Bulk Contact CROSSSECTION of NMOS Transistor CrossSection of CMOS Technology MOS transistors
More informationLecture 11: MOSFET Modeling
Digital Integrated Circuits (83313) Lecture 11: MOSFET ing Semester B, 201617 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,
More informationQuantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.
Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & MixedSignal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationMOSFET. IdVd curve. I DS Transfer curve V G. Lec. 8. Vd=1V. Saturation region. V Th
MOSFET IdVd curve Saturation region I DS Transfer curve Vd=1V V Th V G 1 0 < V GS < V T V GS > V T V Gs >V T & Small V D > 0 I DS WQ inv WC v WC i V V VDS V V G i T G n T L n I D g V D (g conductance
More informationEE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania
1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat AbuTaha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More informationECE606: Solid State Devices Lecture 23 MOSFET IV Characteristics MOSFET nonidealities
ECE66: Solid State evices Lecture 3 MOSFET I Characteristics MOSFET nonidealities Gerhard Klimeck gekco@purdue.edu Outline 1) Square law/ simplified bulk charge theory ) elocity saturation in simplified
More informationScaling Issues in Planar FET: Dual Gate FET and FinFETs
Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology  Cairo 1 Outline Scaling Issues for Planar
More informationnmosfet Schematic Four structural masks: Field, Gate, Contact, Metal. Reverse doping polarities for pmosfet in Nwell.
nmosfet Schematic Four structural masks: Field, Gate, Contact, Metal. Reverse doping polarities for pmosfet in Nwell. nmosfet Schematic 0 y L n + source n + drain depletion region polysilicon gate x z
More informationECE 497 JS Lecture  12 Device Technologies
ECE 497 JS Lecture  12 Device Technologies Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationMicroelectronic Devices and Circuits Lecture 13  Linear Equivalent Circuits  Outline Announcements Exam Two 
6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS V th " VGS vi  I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cutoff. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More informationLecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
More informationMOSFET Capacitance Model
MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small
More informationVirtual Device Simulation. Virtual Process Integration
: CMOS Process and Device Simulation Virtual Device Simulation Virtual Process Integration Dr Zhou Xing Office: S1B1c95 Phone: 67904532 Email: exzhou@ntu.edu.sg Web: http://www.ntu.edu.sg/home/exzhou/teaching//
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationMOSFETs  An Introduction
Chapter 17. MOSFETs An Introduction Sung June Kim kimsj@snu.ac.kr http://helios.snu.ac.kr CONTENTS Qualitative Theory of Operation Quantitative I Relationships Subthreshold Swing ac Response Qualitative
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and MK Lee 1. The purest semiconductor crystals it is possible
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and crosssectional area 100µm 2
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 5: Januar 6, 17 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level
More informationII III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing
II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III  V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band
More informationLongchannel MOSFET IV Corrections
Longchannel MOSFET IV orrections Three MITs of the Day The body ect and its influence on longchannel V th. Longchannel subthreshold conduction and control (subthreshold slope S) Scattering components
More informationChoice of V t and Gate Doping Type
Choice of V t and Gate Doping Type To make circuit design easier, it is routine to set V t at a small positive value, e.g., 0.4 V, so that, at V g = 0, the transistor does not have an inversion layer and
More informationPart 4: Heterojunctions  MOS Devices. MOSFET Current Voltage Characteristics
MOS Device Uses: Part 4: Heterojunctions  MOS Devices MOSCAP capacitor: storing charge, chargecoupled device (CCD), etc. MOSFET transistor: switch, current amplifier, dynamic random access memory (DRAMvolatile),
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationChapter 5 MOSFET Theory for Submicron Technology
Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are
More informationECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University
NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the
More information