# Lecture 11: MOSFET Modeling

Size: px
Start display at page:

Transcription

1 Digital Integrated Circuits (83-313) Lecture 11: MOSFET ing Semester B, Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited; however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed, please feel free to and I will address this as soon as possible.

2 MOSFET Current ing In Digital Electronic Circuits, we used the Shockley for hand-analysis of circuit operation. However, there are many models with varying levels of accuracy to estimate the I-V curves of a MOSFET. In this section, we will overview several models that will come in use throughout this course and your future. 2

3 3 Lecture Content

4 4 Basic MOS s

5 Switch The Switch The most simple MOSFET model is the Switch. V GS > V T R on S D I DS I DS 1/R on 5 V T V GS V DS

6 The Piece-Wise Linear The Switch As we know, when the channel pinches off, the current saturates. I DS This can be depicted with the simple Piece-Wise Linear Switch I DSAT linear saturation The Piece-wise Linear 1/R on V GT V DS 6

7 Adding Channel Length Modulation Channel Length Modulation modeled as a finite output resistance, causes a saturation current dependence on V DS. The Switch The Piece-wise Linear I DSAT 1/λIDSAT I DS D V DS I DSAT I DS Channel Length Modulation λi DSAT S 1/R on -1/λ V GT V DS 7

8 8 Square Law (Shockley) To get a more accurate model, we already are familiar with the Shockley or Square Law. Current is just charge times velocity, so at any point, x, along the channel: I x x Q x Wdx We found that charge can be approximated as: D Q x C ox V GS VCS x VT And the velocity is the mobility times the electrical field: dv x E x n dx The Switch The Piece-wise Linear The Square Law

9 Square Law (Shockley) The Switch So we get: I dx C W V V V dv D n ox GS T At pinch-off (V DS =V GS -V T ), the voltage over the channel is constant, so we get: This is where the Square-Law name comes from. And integrating from source to drain, we get L V DS W 1 I I dx C W V V V dv C V V V V L 2 DS D n ox GS T n ox DS GS T DS 0 0 W I C V V 2L 2 DSAT n ox GS T The Piece-wise Linear The Square Law 9

10 Square Law (Shockley) Replacing V DS with V DSeff =min(v GS -V T, V DS ) we get: 2 W V I C V V V V L 2 DSeff 1 DS n ox GS T DSeff DS The Switch The Piece-wise Linear The Square Law 10

11 The Velocity Saturation However, when looking at a short channel device, we see a linear dependence on V GS. This can be attributed to Velocity Saturation. sat 5 10 m s The Switch The Piece-wise Linear The Square Law The V-Sat 11

12 The Velocity Saturation A good approximation of the mobility curve is: 1 crit sat crit crit The Switch The Piece-wise Linear The Square Law The V-Sat 12 For continuity: crit After integration, we get: 2 sat C W I V V V 1 L 2 n ox DS DS GS T DS V DS L 2 crit V

13 The Velocity Saturation The Switch 13 This is hard to use, but we can reach an important conclusion. We found that: And we know that for a velocity saturated device: Equating, we get: V DSAT C W I V V V 1 L 2 n ox DS DS GS T DS V DS L 2 V V L GS T crit V V L GS T crit crit V I DS WCox VGS VDSAT VT sat DSAT crit GT GS T V L V V V pinch off V L V L vel sat DSAT crit GT crit The Piece-wise Linear The Square Law The V-Sat

14 The Unified for Hand Analysis A few simple estimations will make the V-Sat model more user-friendly: The mobility is piecewise linear, saturating at ξ>ξ crit /2 V DSAT is piecewise linear, saturating at V DSAT =ξ crit L/2, when V GT >ξ crit L/2 The Switch The Piece-wise Linear The Square Law The V-Sat The Unified 14

15 The Unified for Hand Analysis This brings us to the Unified : 2 W V DSeff I C V V V 1 V L 2 DS n ox GS T DSeff DS V min V V, V, V DSeff GS T DS DSAT V DSAT crit 2 L crit 2 sat The Switch The Piece-wise Linear The Square Law The V-Sat The Unified 15

17 17 VT* Sometimes we want to use a really simple model. We can assume that if the transistor is on, it s velocity saturated. 2 V DSAT IDS kn VGS VT VDSAT 2 I DS VDSAT k V V V 2 * VT n GS T DSAT k V V V V V * 0 VGS VT * * n GS T DSAT GS T The Switch The Piece-wise Linear The Square Law The V-Sat The Unified The VT*

18 The Alpha Power Law Sakurai found that by changing the exponent of the square law, a better fit can be found with simple calculations. Shockley (α=2) Alpha (α=1.3) W I C V V 2L DSAT n ox GS T The Switch The Piece-wise Linear The Square Law The V-Sat The Unified The VT* The Alpha Power Law 18

19 BSIM The main model used by simulators today is the BSIM4 model. This model uses hundreds of parameters to achieve a good fit. This model takes into account all known physical effects, as well as many fitting parameters. The Switch The Piece-wise Linear The Square Law The V-Sat The Unified The VT* The Alpha Power Law BSIM 19

20 Newer s BSIM Group Webpage: Compact Coalition (CMC) Webpage: Newer BSIM s: BSIM6 Bulk CMOS BSIMSOI - SoI model standardized in 2001 (built on BSIM3.3) BSIM-CMG multi-gate FETs (FinFet, Nanowire) written in Verilog-A BSIM-IMG Independent Multi-Gate for UTBB-SoI EKV : Developed in 1995 to provide accuracy even in subthreshold PSP: Standard for current bulk CMOS The Switch The Piece-wise Linear The Square Law The V-Sat The Unified The VT* The Alpha Power Law BSIM And more 20

21 21 Threshold Voltage Revisited

22 Energy Band Diagrams To understand the threshold voltage and other secondary effects of the MOS device, we often use energy band diagrams. The first approach is looking in from the gate: 22

23 Energy Band Diagrams The second approach is looking from the source to the drain. 23

24 Threshold Voltage - Basic Theory Basic Theory The basic definition of threshold voltage is the gate voltage (V G ) required to invert the channel V Q OX T 0 MS 2 F Cox Q C dep ox Q 2qN 2 dep A si F N A F T ln T n i kt q 24

25 Body The appearance of a voltage difference between the source and body (V SB ) is known as The Body This can be modeled by the additional charge that needs to be depleted. Basic Theory Classic Body Q 2qN 2 V dep A si F SB V V 0 2 V 2 T T F SB F 25 V Q ox T 0 MS 2 F Cox Q dep0 C ox 2q si N A C ox

26 Modern Body A different approach is to look at the capacitive voltage divider between the gate and body (C GB ) Basic Theory Classic Body Modern Body C dep s W d max V S S V G G C C oxe 26 Q C V V V C V V inv oxe GS CS T 0 dep SB CS C dep Coxe VGS nvcs VT 0 n 1 1 C oxe 3T W oxe d max V B B C dep

27 Modern Body This can be shown to redefine V T as: C V V V V C ( ) dep T SB T0 SB oxe Basic Theory Classic Body Modern Body In modern technologies, C dep /C oxe is a constant, so V T is linearly dependent on V SB! 27

28 Poly Depletion and Channel Depth Basic Theory The threshold voltage is affected by two additional factors that we have disregarded until now: Polysilicon Depletion Since polysilicon is, itself, a semiconductor, the depletion layer into the poly effectively increases the oxide thickness. Classic Body Modern Body Channel Depth Since the channel is not a 2-dimensional line along the surface, the oxide thickness is essentially increased. n Cdep 1 1 C oxe 3T W oxe d max 28

29 Hot Carrier s Electrons can get so fast that they can tunnel into the gate oxide and increase the threshold voltage. V OX T 0 MS 2 F Cox This is a reliability issue as it happens over time. Q Q C dep ox Basic Theory Classic Body Modern Body Hot Carriers 29

30 V T Roll Off (Short Channel ) As channel length is reduced, effective channel length is reduced by depletion regions. Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off A trapezoid is created under the gate, dividing the channel into the region controlled by the gates and by the drain. 65nm technology. t ox =1.2nm V dd =1V K. Goto et al., IEDM In essence, V T is reduced.

31 DIBL (Drain Induced Barrier Lowering) In short channels, the barrier of the channel is essentially lowered, as the drain causes the energy band to drop closer to the source. This is exponentially dependent on V DS. Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL 31 V V V 0.4 T T,long DS C C d oxe

32 Roll Off / DIBL combined Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL 32

33 Reverse Short Channel (RSCE) V T actually increases at channel lengths a bit higher than minimum Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL RSCE 33

34 How to Measure VT There are various ways to measure V T One classic way takes a small V DS and sweeps V GS. Basic Theory Classic Body Modern Body 2 Id k ( Vgs Vt ) Vds 0.5V ds Vgs Vt So we can find the V GS at which the linear part crosses I ds =0. V T,gm V DS =50mV Hot Carriers VT Roll-Off DIBL RSCE Measuring VT 34

35 How to Measure VT One of the more common ways is to find the V GS at which I DS =100 na x W/L. For V T,lin, set a low V DS (V DS =50mV) For V T,sat set a high V DS (V DS =V DD ) Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL RSCE Measuring VT 35

36 OP and MP in Spectre Basic Theory Classic Body Modern Body Hot Carriers VT Roll-Off DIBL RSCE Measuring VT 36

37 Further Reading J. Rabaey, Digital Integrated Circuits 2003, Chapters 2.5, Weste, Harris CMOS VLSI Design, Chapter 7 C. Hu, Modern Semiconductor Devices for Integrated Circuits, 2010, Chapters 4-7 Tzividis, et al. Operation and ing of MOS Transistor Chapters 1-5 E. Alon, Berkeley EE-141, Lecture 9 (Fall 2009) M. Alam, Purdue ECE-606 lectures (2009) nanohub.org A. B. Bhattacharyya Compact MOSFET models for VLSI design, 2009, T. Sakurai, Alpha Power-Law MOS JSSC Newsletter Oct 2004 Managing Process Variation in Intel s 45nm CMOS Technology, Intel Technology Journal, 2008 Berkeley BSIM User s Manual 37

### Lecture 4: Technology Scaling

Digital Integrated Circuits (83-313) Lecture 4: Technology Scaling Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 2 April 2017 Disclaimer: This course was prepared, in its

### The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

### CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

### ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

### Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

### Practice 3: Semiconductors

Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

### Lecture 4: CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

### EE5311- Digital IC Design

EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM

### MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

### Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

### CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

### The Devices: MOS Transistors

The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

### Nanoscale CMOS Design Issues

Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal

### MOS Transistor I-V Characteristics and Parasitics

ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

### MOSFET: Introduction

E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

### ECE 305: Fall MOSFET Energy Bands

ECE 305: Fall 2016 MOSFET Energy Bands Professor Peter Bermel Electrical and Computer Engineering Purdue University, West Lafayette, IN USA pbermel@purdue.edu Pierret, Semiconductor Device Fundamentals

### Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

### Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

### The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

### EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold

### Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

### ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

### Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar

### EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

### EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

### Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

### MOS Transistor Theory

CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

### VLSI Design The MOS Transistor

VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V

### HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7

HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2 What do digital IC designers need to know? 5 EE4 EECS4 6 3 0< V GS - V T < V DS Pinch-off 7 For (V GS V T )

### ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

### Semiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5

Semiconductor Devices C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Global leader in environmental and industrial measurement Wednesday 3.2. afternoon Tour around facilities & lecture

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!

### ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 6, 01 MOS Transistor Basics Today MOS Transistor Topology Threshold Operating Regions Resistive Saturation

### Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

### Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order

### A Multi-Gate CMOS Compact Model BSIMMG

A Multi-Gate CMOS Compact Model BSIMMG Darsen Lu, Sriramkumar Venugopalan, Tanvir Morshed, Yogesh Singh Chauhan, Chung-Hsun Lin, Mohan Dunga, Ali Niknejad and Chenming Hu University of California, Berkeley

### EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

### Lecture #27. The Short Channel Effect (SCE)

Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )

### The Devices. Jan M. Rabaey

The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

### ECE-305: Spring 2016 MOSFET IV

ECE-305: Spring 2016 MOSFET IV Professor Mark Lundstrom Electrical and Computer Engineering Purdue University, West Lafayette, IN USA lundstro@purdue.edu Lundstrom s lecture notes: Lecture 4 4/7/16 outline

### Microelectronics Part 1: Main CMOS circuits design rules

GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

### Lecture 9: Interconnect

Digital Integrated Circuits (83-313) Lecture 9: Interconnect Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 23 May 2017 Disclaimer: This course was prepared, in its entirety,

### ECE315 / ECE515 Lecture-2 Date:

Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode

### Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

### Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

### The Gradual Channel Approximation for the MOSFET:

6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

### ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

### MOSFET. Id-Vd curve. I DS Transfer curve V G. Lec. 8. Vd=1V. Saturation region. V Th

MOSFET Id-Vd curve Saturation region I DS Transfer curve Vd=1V V Th V G 1 0 < V GS < V T V GS > V T V Gs >V T & Small V D > 0 I DS WQ inv WC v WC i V V VDS V V G i T G n T L n I D g V D (g conductance

### ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um

### Section 12: Intro to Devices

Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

### Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007

### CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

### Lecture 04 Review of MOSFET

ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

### Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)

Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture

### Technische Universität Graz. Institute of Solid State Physics. 11. MOSFETs

Technische Universität Graz Institute of Solid State Physics 11. MOSFETs Dec. 12, 2018 Gradual channel approximation accumulation depletion inversion http://lampx.tugraz.at/~hadley/psd/l10/gradualchannelapprox.php

### Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

### MOS Device Modeling. C.K. Ken Yang UCLA Courtesy of Agilent eesoft EE 215B

MOS Device Modeling C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of Agilent eesoft 1 Overview Reading Rabaey 3.3 W&H 2.2-2.4 Overview This class will look at the iv and CV characteristics of an MOS device

### MOS Transistor Theory

MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

### P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

### LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and

### Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture

### Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

### Nanometer Transistors and Their Models. Jan M. Rabaey

Nanometer Transistors and Their Models Jan M. Rabaey Chapter Outline Nanometer transistor behavior and models Sub-threshold currents and leakage Variability Device and technology innovations Nanometer

### MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste

### Semiconductor Integrated Process Design (MS 635)

Semiconductor Integrated Process Design (MS 635) Instructor: Prof. Keon Jae Lee - Office: 응용공학동 #4306, Tel: #3343 - Email: keonlee@kaist.ac.kr Lecture: (Tu, Th), 1:00-2:15 #2425 Office hour: Tues & Thur

### FIELD-EFFECT TRANSISTORS

FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation

### ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the

### ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current

### EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

### SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

### CMOS Inverter (static view)

Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

### ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

### Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

### MOS Transistor. EE141-Fall 2007 Digital Integrated Circuits. Review: What is a Transistor? Announcements. Class Material

EE-Fall 7 igital Integrated Circuits MO Transistor Lecture MO Transistor Model Announcements Review: hat is a Transistor? Lab this week! Lab next week Homework # is due Thurs. Homework # due next Thurs.

### ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

### EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

### Compact Modeling of Semiconductor Devices: MOSFET

Compact Modeling of Semiconductor Devices: MOSFET Yogesh S. Chauhan Assistant Professor and Ramanujan Fellow Nanolab, Department of Electrical Engineering IIT Kanpur Email: chauhan@iitk.ac.in Homepage

### EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150

### N Channel MOSFET level 3

N Channel MOSFET level 3 mosn3 NSource NBulk NSource NBulk NSource NBulk NSource (a) (b) (c) (d) NBulk Figure 1: MOSFET Types Form: mosn3: instance name n 1 n n 3 n n 1 is the drain node, n is the gate

### EE 560 MOS TRANSISTOR THEORY

1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:

### Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007

6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 28-1 Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007 Contents: 1. Second-order and

### MOSFET Capacitance Model

MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small

### Introduction and Background

Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments

### The PSP compact MOSFET model An update

The PSP compact MOSFET model An update Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen NXP Semiconductors Ronald van Langevelde Philips Research Europe Gennady Gildenblat, Weimin Wu, Xin Li, Amit Jha,

### MOSFET Physics: The Long Channel Approximation

MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The

### Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias

ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 5: Januar 6, 17 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level

### Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

### RFIC2017 MO2B-2. A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits

A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits M. Baraani Dastjerdi and H. Krishnaswamy CoSMIC Lab, Columbia University, New

### Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

### ! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

### Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

### EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION

### Advanced Compact Models for MOSFETs

Advanced Compact Models for MOSFETs Christian Enz, Carlos Galup-Montoro, Gennady Gildenblat, Chenming Hu, Ronald van Langevelde, Mitiko Miura-Mattausch, Rafael Rios, Chih-Tang (Tom) Sah Josef Watts (editor)

### VLSI Design and Simulation

VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage

### The Devices. Devices

The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors