HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7
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1 HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2
2 What do digital IC designers need to know? 5 EE4 EECS4 6 3
3 0< V GS - V T < V DS Pinch-off 7 For (V GS V T ) < V DS, the effective drain voltage and current saturate: Of course, real drain current isn t totally independent of V DS For example, approx. for channel-length modulation: 8 4
4 Cutoff: V GS -V T < 0 Linear (Resistive): V GS -V T > V DS Saturation: 0 < V GS -V T < V DS 9-4 x 0 6 V GS = 2.5 V 5 I D (A) 4 3 Resistive Saturation V GS = 2.0 V V DS = V GS - V T Quadratic Relationship 2 V GS =.5 V V GS =.0 V V DS (V) 0 5
5 x 0 Early V = 2.5 V GS Saturation 2 V GS = 2.0 V.5 I D (A) V GS =.5 V Linear Relationship 0.5 V GS =.0 V V DS (V) Velocity saturates due to carrier scattering effects n ( m / s ) sat = 0 5 Constant velocity Constant mobility (slope = μ) c (V/μm) 2 6
6 I D Long-channel device V GS = V DD Short-channel device V DSAT V GS - V T V DS 3 6 x x I D (A) 4 3 quadratic I D (A).5 linear V (V) GS Long Channel (L=2.5μm) 0.5 quadratic V (V) GS Short Channel (L=0.25μm) 4 7
7 Approximate velocity: Continuity requires that: Integrating to find the current again: 5 I D (A) 6 x 0-4 V GS = 2.5 V Resistive Saturation V GS = 2.0 V V DS = V GS - V T V GS =.5 V V GS =.0 V I D (A) -4 V DSAT 2.5 x 0 V GS = 2.5 V Resistive Velocity Saturation V GS -V T V GS = 2.0 V V GS =.5 V V GS =.0 V V DS (V) V DS (V) Long Channel (L=2.5μm) W/L=.5 Short Channel (L=0.25μm) 6 8
8 Exact behavior of transistor in velocity sat. somewhat challenging if want simple/easy to use models So, many different models developed over the years v-sat, alpha, unified, V T *, etc. Simple model for manual analysis desirable Assume velocity perfectly linear until sat Assume V DSAT constant 7 Assume velocity perfectly linear until hit sat n ( m / s ) sat = 0 5 Constant velocity c = sat /μ (V/μm) 8 8 9
9 Assume V DSAT = c L when (V GS V T ) > c L V DSAT (V) Actual V DSAT c L c L V GS -V T (V) 9 define V GT = V GS V T G for V GT 0: I D = 0 S D for V GT 0: I D B with V DS,eff = min (V GT, V DS, V D,VSAT ) 20 0
10 Define V GT = V GS V T, V D,VSAT = c L x 0 I D (A) 2.5 Linear V DS = V D,VSAT Velocity Saturation 0.5 V GT = V D,VSAT V DS = V GT V DS (V) Saturation 2-4 x V DS =V D,VSAT 2.5 I D (A) 0.5 V DS =V GT V (V) DS 22
11 If device always operates in velocity sat.: V T * model: Good for first cut, simple analysis 23 V Textbook: page
12 -4 x 0 0 VGS = -.0V All variables negative VGS = -.5V I prefer to work with absolute values I D (A) -0.6 VGS = -2.0V -0.8 VGS = -2.5V V (V) DS 25 EE4 EECS4 26 3
13 G = C GCS + C GSO = C GCD + C GDO S D = C diff B = C GCB = C diff 27 Capacitance (per area) from gate across the oxide is W L C ox, where C ox = ox /t ox 28 4
14 Distribution between terminals is complex Capacitance is really distributed Useful models lump it to the terminals Several operating regions: Way off, off, transistor linear, transistor saturated 29 When the transistor is off, no carriers in channel to form the other side of the capacitor. Substrate acts as the other capacitor terminal Capacitance becomes series combination of gate oxide and depletion capacitance 30 5
15 When V GS < V T, total C GCB much smaller than W L C ox Usually just approximate with C GCB = 0 in this region. (If V GS is very negative (for NMOS), depletion region shrinks and C GCB goes back to ~W L C ox ) 3 Channel is formed and acts as the other terminal C GCB drops to zero (shielded by channel) Model by splitting oxide cap equally between source and drain Changing either voltage changes the channel charge 32 6
16 Changing source voltage doesn t change V GC uniformly E.g. V GC at pinch off point still V TH Bottom line: C GCS 2/3 W L C ox Drain voltage no longer affects channel charge Set by source and V DS_sat If change in charge is 0, C GCD =
17 C gate vs. V GS (with V DS = 0) C gate vs. operating region 35 Off/Lin/Sat C GSO = C GDO = C O W
18 Fringing fields n + n + Cross section C OV not just from metallurgic overlap get fringing fields too Typical value: ~0.2fF W(in μm)/edge 37 9
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