# EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

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1 EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation

2 Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins, Rise & Fall Times, Inverter Delay CMOS Inverters: Rabaey 1.3., 5 (Kang & Leblebici, and ) Amirtharajah, EEC 116 Fall 011 3

3 Review: Inverter oltage Transfer Curve oltage transfer curve (TC): plot of output voltage out vs. input voltage in in Inverter out dd out ideal actual Ideal digital inverter: When in=0, out=dd When in=dd, out=0 0 in dd Sharp transition region Amirtharajah, EEC 116 Fall 011 4

4 Review: Actual Inverter Output Levels OH and OL represent the high and low output voltages of the inverter OH OH = output voltage when in = 0 ( Output High) out OL = output voltage when in = 1 ( Output Low) OL 0 in dd Ideally, OH = dd OL = 0 Amirtharajah, EEC 116 Fall 011 5

5 Review: OL and OH In transfer function terms: OL = f( OH ) OH out OH = f( OL ) f = inverter transfer function OL OL in OH dd Difference ( OH - OL ) is the voltage swing of the gate Full-swing logic swings from ground to dd Other families with smaller swings Amirtharajah, EEC 116 Fall 011 6

6 Review: Inverter Switching Threshold Inverter switching threshold: OH out=in Point where voltage transfer curve intersects line out=in out OL in M dd Represents the point at which the inverter switches state Normally, M dd/ Sometimes other thresholds desirable Amirtharajah, EEC 116 Fall 011 7

7 TC Mathematical Definitions OH is the output high level of an inverter OH = TC( OL ) OL is the output low level of an inverter OL = TC( OH ) M is the switching threshold M = IN = OUT IH is the lowest input voltage for which the output will be the input (worst case 1 ) dtc( IH )/d IH = -1 IL is the highest input voltage for which the output will be the input (worst case 0 ) dtc( IL )/d IL = -1 Amirtharajah, EEC 116 Fall 011 8

8 Noise Margin and Delay Definitions NM L is the difference between the highest acceptable 0 and the lowest possible 0 NM L = IL OL NM H is the difference between the lowest acceptable 1 and the highest possible 1 NM H = OH IH t PHL is the propagation delay from the 50% point of the input to the output when the output goes from high to low t PLH is the propagation delay from the 50% point of the input to the output when the output goes from low to high t P is the average propagation delay t R is the rise time (usually 10% to 90%) t F is the fall time (usually 90% to 10%) Amirtharajah, EEC 116 Fall 011 9

9 CMOS Inverter Complementary NMOS and PMOS devices In steady-state, only one device is on (no static power consumption) in in=1: NMOS on, PMOS off out= OL = 0 in=0: PMOS on, NMOS off out= OH = dd Ideal OL and OH! Ratioless logic: output is independent of transistor sizes in steady-state dd Gnd out Amirtharajah, EEC 116 Fall

10 CMOS Inverter: TC PMOS NMOS in =4 Drain current I DS in =3 in = in =1 dd out out = DS dd 0 1 in 3 4 Output goes completely to dd and Gnd Sharp transition region Amirtharajah, EEC 116 Fall

11 CMOS Inverter Operation NMOS transistor: Cutoff if in < TN Linear if out < in TN Saturated if out > in TN PMOS transistor in out Cutoff if ( in - ) > TP in > + TP Linear if ( out - )> in - - TP out > in - TP Sat. if ( out - )< in - - TP out < in - TP Amirtharajah, EEC 116 Fall 011 1

12 CMOS Inverter TC: Device Operation P linear N cutoff P cutoff N linear P linear N sat P sat N sat P sat N linear Amirtharajah, EEC 116 Fall

13 CMOS Inverter TC: Device Sizing out p = n p =5 n Increase W of PMOS p increases TC moves to right Increase W of NMOS n increases TC moves to left p =0. n For M = / n = p W n W p in Amirtharajah, EEC 116 Fall

14 Effects of M adjustment Result from changing p / n ratio: Inverter threshold M / Rise and fall delays unequal Noise margins not equal Reasons for changing inverter threshold Want a faster delay for one type of transition (rise/fall) Remove noise from input signal: increase one noise margin at expense of the other Interfacing other types of logic (with different swings) Amirtharajah, EEC 116 Fall

15 CMOS Inverter: IL Calculation KCL (NMOS saturation, PMOS linear): n p ( GS, n T 0, n ) = ( GS, p T 0, p ) DS, n [ ] Differentiate and set dout/din to 1 p DS, p p ( ) = ( )( ) ( ) in T 0, n [ ] in ( ) ( ) d out dout = + ( ) ( ) n in T 0, n p in T 0, p n d T 0, p ( ) = ( + ) in out out IL T0, n p out IL T0, p out out d in IL = out + T 0, p + RT 0, n 1+ Solve simultaneously with KCL to find IL R = R n p Amirtharajah, EEC 116 Fall

16 n KCL: n n CMOS Inverter: IH Calculation [ ( ) ] p = ( ) GS, n T 0, n DS, n DS, n Differentiate and set dout/din to 1 GS, p [ ( ) ] p = ( ) in T 0, n out out in T 0, p T 0, p ( ) ( ) out out + = in d d T 0, n out out p in din din IH n + = ( ) ( ) = out + IH T 0, p + T0, p 1+ R p IH ( + ) out T 0, n R R = T0, p n p T 0, p Solve simultaneously with KCL to find IH Amirtharajah, EEC 116 Fall

17 CMOS Inverter: M Calculation KCL (NMOS & PMOS saturated): n n ( ) p = ( ) GS, n T 0, n GS, p T 0, p ( ) p = ( ) in T 0, n in T 0, p Solve for M = in = out M = T 0, n + 1 R 1+ ( + ) 1 R T 0, p = Amirtharajah, EEC 116 Fall R n p

18 CMOS Inverter: Achieving Ideal M TH = T 0, n + 1 Ideally, M = / R 1+ ( + ) 1 R T 0, p R, ideal = = R + + n p T 0, p T 0, n Assuming T0,n = T0,p, W L p μn = W μ p L R, ideal =1.5 n Amirtharajah, EEC 116 Fall

19 CMOS Inverter: IL and IH for Ideal M Assuming T0,n =- T0,p, and R = 1, 1 IL = IH = 5 8 IL ( 3 ) T 0 ( ) + = IH T 0 NM = = L IL OL IL NM = = = H OH IH IH IL Amirtharajah, EEC 116 Fall 011 0

20 MOSFET Scaling Effects Rabaey Section 3.5 (Kang & Leblebici Section 3.5) Scaling provides enormous advantages Scale linear dimension (channel length) by factor S > 1 Better area density, yield, performance Two types of scaling Constant field scaling (full scaling) A = A/S ; L = L/S; W = W/S; I D = I D /S; P = P/S ; dd = dd /S Power Density P /A = stays the same Change these two Constant voltage scaling A = A/S ; L = L/S; W = W/S; I D = I D *S; P = P*S; dd = dd Power Density P /A = S 3 *P (Reliability issue) This changed as well Amirtharajah, EEC 116 Fall 011 1

21 Short Channel Effects As geometries are scaled down T (effective) goes lower Effective channel length decreases Sub-threshold Ids occurs Current goes from drain to source while gs < t Tox is scaled which can cause reliability problems Can t handle large g without hot electron effects Changes the t when carriers imbed themselves in the oxide Interconnects scale Electromigration and ESD become issues Amirtharajah, EEC 116 Fall 011

22 MOSFET Capacitances Rabaey Section 3.3 (Kang & Leblebici Section 3.6) Oxide Capacitance Gate to Source overlap Gate to Drain overlap Gate to Channel Junction Capacitance Source to Bul junction Drain to Bul junction Amirtharajah, EEC 116 Fall 011 3

23 Oxide Capacitances: Overlap source L drawn drain x d Overlap capacitances Gate electrode overlaps source and drain regions x d is overlap length on each side of channel L eff = L drawn x d (effective channel length) Overlap capacitance: C = C = C Wx Assume x d equal on both sides GSO GDO ox d Amirtharajah, EEC 116 Fall 011 4

24 Total Oxide Capacitance Total capacitance consists of components Overlap capacitance Channel capacitance Cutoff: C gs source C gb C gd drain No channel connecting to source or drain C GS = C GD = C ox Wx d C GB = C ox WL eff Total Gate Capacitance = C G = C ox WL Amirtharajah, EEC 116 Fall 011 5

25 Oxide Capacitances: Channel Linear mode Channel spans from source to drain Channel Capacitance split equally between S and D C GS 1 C 1 C WL = CoxWLeff GD ox eff Total Gate capacitance C G = C ox WL Saturation regime Channel is pinched off: Channel Capacitance -- C = Wx GD d C ox GS ox Amirtharajah, EEC 116 Fall = C = C WL + 3 Total Gate capacitance: C G = /3 C ox WL eff + x d WC OX eff C OX Wx C GB d = 0 C GB = 0

26 Oxide Capacitances: Channel C g,total (no overlap, x d = 0) Amirtharajah, EEC 116 Fall 011 7

27 Junction Capacitance Reverse-biased P-N junctions! Capacitance depends on reverse-bias voltage. Amirtharajah, EEC 116 Fall 011 8

28 Amirtharajah, EEC 116 Fall Junction Capacitance a d a d j N N N N q A C + = 0 ε For a P-N junction: a d a d Si j N N N N q C + = 0 0 ε If =0, cap/area = m j j AC C = General form: m = grading coefficient (0.5 for abrupt junctions) (0.3 for graded junctions)

29 Junction Capacitance Junction with substrate Bottom area = W * L S (length of drain/source) Total cap = C j Junction with sidewalls Channel-stop implant Perimeter = L S + W Area = P * X j Total cap = C jsw Total junction cap C = C j + C jsw Amirtharajah, EEC 116 Fall

30 Junction Capacitance oltage Equivalence Factor Creates an average capacitance value for a voltage transition, defined as ΔQ/Δ AC 1 m 1 m j0 0 1 C eq = 1 1 = AK ( )( ) eq j0 1 m C K eq = (abrupt junction only) 0 ( ) ( ) C = AK C + db eq PX K C j0 j eqsw jsw0 Amirtharajah, EEC 116 Fall

31 Example: Junction Cap Consider the following NMOS device Substrate doping: N A = cm -3 Source/drain doping: N D = x 10 0 cm -3 Channel-stop doping: 10X substrate doping Drain length L D = 1um Transistor W = 10um Junction depth Xj = 0.5um, abrupt junction Find capacitance of drain-bul junction when drain voltage = 3 Amirtharajah, EEC 116 Fall 011 3

32 CMOS Inverters Next Time: AC Characteristics AC Characteristics: Designing for speed Amirtharajah, EEC 116 Fall

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