! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications


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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model! First Order Capacitor Summary! Capacitance Implications Review: nmos IV Characteristics! V! W $ GS V th $ # &!! V DS $ # " nkt /q % I S # &e e & $ " kt /q % " L % # &( + λv DS ) " % V GS V Tn Subthreshold µ n x W ( I D = L ( V V (V ) GS Tn SB DS DS )(+ λ V DS ) 3 V GS > V Tn,V DS < V GS Linear µ n x W L V V (V ) GS Tn SB (+ λ V DS ) V GS > V Tn,V DS V GS V Tn Saturation, v sat C OX W ( V GS V th ) V / dsat E y > E cn (short channel) Velocity Saturation Simplified Design Flow! Design a circuit to perform a function with specified minimum speed and optimized power (minimized with an upper bound) " Zero order model to design topology today " First order model to meet speed spec " Rise/fall times, propogation delay, gate capacitance, output stage equivalent resistance " Transistor IV curves " Iterative SPICE simulation tweak knobs to optimize for power (switching (dynamic), leakage (static), etc.) 3 MOSFET Parasitic Capacitance Capacitance Roundup! C GS =S +C GSO! C GD =D +C GDO! C GB =B! C SB =C diff! C DB =C diff! Any two conductors separated by an insulator form a parallelplate capacitor! Two types " Extrinsic Outside the box (e.g. junction, overlap) " Intrinsic Inside the box (e.g. gatetochannel) intrinsic extrinsic 5 6
2 Overlap Extrinsic! gate/source and gate/drain overlap Overlap Capacitance 8 Overlap! Length of overlap L D = L M L eff Overlap Capacitance L M L D C = ε r ε 0 A d L M L D L eff = ε ox t ox L eff 9 0 Overlap Capacitance Overlap Capacitance L M L D C = ε r ε 0 A d L M L D C = ε r ε 0 A d L eff C OX = ε OX t OX L eff C OX = ε OX t OX = ε ox t ox = ε ox t ox = x = x = C GSO = C GDO
3 Overlap Capacitance! It turns out that fringing field lines add significantly to the total capacitance! Estimates of the fringing field capacitances based on measurements are normally used! The gatetodrain overlap capacitances are generally given as measured parameters in the MOSFET model files! The values are perwidth values Overlap Capacitance Name Model Parameters Units LEVEL Model type (,, or 3) CBD Bulkdrain zerobias pn cap (not used) F CBS Bulksource zerobias pn cap (not used) F CJ Bulk pn zerobias bottom cap/area F/m** CJSW Bulk pn zerobias perimeter cap/length F/m MJ Bulk pn bottom grading coefficient MJSW Bulk pn sidewall grading coefficient FC Empirical bulk pn forwardbias cap coefficient CGSO Gatesource overlap cap/channel width F/m CGDO Gatedrain overlap cap/channel width F/m CGBO Gatebulk overlap cap/channel width F/m NSUB Substate doping density /cm**3 NSS Surfacestate density /cm** NFS Fast surfacestate density /cm** TOX Oxide thickness m TPG Gate material type: + = opposite of substrate,  = same as substrate, 0 = aluminum XJ Metallurgical junction depth m Scales with Width (W) 3 Extrinsic n + n + 6 (Bottom) n + n + N D + V = Ext Bias > V SB, V DB! * : Sidewall, sw! 5: (Bottom), 7 8 3
4 (Bottom) Sidewall n + n + N D 0sw = ε siq N A(sw) N D N A (sw)+ N D φ 0 (F/cm ) + V = Ext Bias > V SB, V DB (F/cm) 0 = ε si x d = ε siq N A N D N A + N D φ 0 Zerobias capacitance (F/cm ) 9 0 C diff = WY + sw ( Y +W ) Voltage Dependence Name Model Parameters Units LEVEL Model type (,, or 3) CBD Bulkdrain zerobias pn cap (not used) F CBS Bulksource zerobias pn cap (not used) F CJ Bulk pn zerobias bottom cap/area F/m** CJSW Bulk pn zerobias perimeter cap/length F/m MJ Bulk pn bottom grading coefficient MJSW Bulk pn sidewall grading coefficient FC Empirical bulk pn forwardbias cap coefficient CGSO Gatesource overlap cap/channel width F/m CGDO Gatedrain overlap cap/channel width F/m CGBO Gatebulk overlap cap/channel width F/m (0) = A S,D 0 A C S,D j0 + V S,D m NSUB Substate doping density /cm**3 NSS Surfacestate density /cm** NFS Fast surfacestate density /cm** TOX Oxide thickness m TPG Gate material type: + = opposite of substrate,  = same as substrate, 0 = aluminum XJ Metallurgical junction depth m Scales with Junction area or width (0) = A D 0 A C D j0 + V D m Notation simplification: Assume we re just working with the drain 3 Penn ESE 570 Spring 07  Khanna
5 Voltage Dependence Voltage Dependence (0) = A D 0 A C D j0 + V D m Voltage Dependent Voltage Independent Approximation (0) = A D 0 A C D j0 + V D m Voltage Dependent Voltage Independent Approximation Φ 0 0 V m + V + V Φ 0 0 V m + V + V K eq Where V V D Possible drain potential range Where V V D Possible drain potential range 0 K eq Where 0<K eq < Penn ESE 570 Spring 07  Khanna 5 Penn ESE 570 Spring 07  Khanna 6 Voltage Dependence Junction (SW) Capacitance Voltage Dependence (0) = A D 0 A C D j0 + V D m Voltage Dependent Voltage Independent Approximation sw (0) = 0sw sw P C S,D j0sw + V S,D 0sw m sw Voltage Dependent Voltage Independent Approximation Φ 0 0 V m + V + V K eq Φ sw (V ) P D 0sw 0sw + V sw V m sw + V 0sw 0sw sw K eq,sw Where V V D Possible drain potential range Where V V D Possible drain potential range 0 K eq Where 0<K eq < 0 K eq Where 0<K eq < Penn ESE 570 Spring 07  Khanna 7 Penn ESE 570 Spring 07  Khanna 8 Example: Example:! Determine the total junction capacitance at the drain, i.e. C db, for the MOSFET and spice model parameters given below. Source and drain are surrounded by p + channelstop. The p substrate is biased at 0V and the drain voltage range is 0.5V to 5V. Φ 0 0 V m + V + V Φ sw (V ) P D 0sw 0sw + V sw V m sw + V 0sw 0sw sw Penn ESE 570 Spring 07  Khanna 9 Penn ESE 570 Spring 07  Khanna 30 5
6 Diode Capacitance! When a reverse voltage is applied to a PN junction, a depletion region containing almost no charge carriers is generated and acts similarly to the dielectric of a capacitor.! The depletion region increases in width as the reverse voltage across it increases.! If we imagine that the diode capacitance can be likened to a parallel plate capacitor, then as the plate spacing (i.e. the depletion region width) increases, the capacitance should decrease.! Increasing the reverse bias voltage across the PN junction therefore decreases the diode capacitance.! Worst case is in zerobias case Example: Φ 0 0 V m + V + V Φ sw (V ) P D 0sw 0sw + V sw V m sw + V 0sw 0sw sw 3 Penn ESE 570 Spring 07  Khanna 3 Capacitance Roundup! C GS =S +C GSO! C GD =D +C GDO! C GB =B! C SB =C diff! C DB =C diff Intrinsic intrinsic extrinsic 33 GatetoChannel Capacitance! Looks like parallel plate capacitance! Two components: " What is? " What is C GB? GatetoChannel Capacitance! Looks like parallel plate capacitance! Two components: Case: Strong Inversion " " C GB =0 = x WL eff
7 GatetoChannel Capacitance! Looks like parallel plate capacitance! Two components: Case: Strong Inversion " Split evenly between S and D " C GB =0 = x WL eff S = D = xwl eff GatetoSource Capacitance! Channel + Overlap C GS = S + C GSO C GS = C OX + C WL " OX eff = C OX W L L % M eff $ '+ # & C WL OX eff C GS = C OX WL M GatetoDrain Capacitance Channel Evolution: Weak Inversion! Channel + Overlap C GD = D + C GDO C GD = C OX + C WL " OX eff = C OX W L M L eff % $ '+ # & C WL OX eff C GD = C OXWL M 39 0 Channel Evolution: Weak Inversion Channel Evolution: Weak Inversion! What happens to capacitance here? " Capacitor plate distance?! Capacitance becomes dominated by GatetoBody capacitance (S,D =0)! Gatetobody capacitance drops as V GS increases toward V th 7
8 Capacitance vs V GS (V DS =0) Saturation Capacitance? 0.5 S =D B V GS Increasing V GS 3 Saturation Capacitance? Saturation Capacitance! Source end of channel in inversion! Voltage at drain end of channel at or below threshold! Capacitance shifts to source " Total capacitance reduced 0.5 S D 0 V DS /(V GS V T ) (/3) 5 6 Capacitance Roundup First Order Capacitance Summary! C GS =S +C GSO! C GD =D +C GDO! C GB =B! C SB =C diff Simplifiy: what is C G? Subthreshold Linear Saturation B S D C G! C DB =C diff intrinsic extrinsic 7 8 8
9 First Order Capacitance Summary Subthreshold B S D C G Linear 0 C OX WL/ C OX WL/ Saturation First Order Capacitance Summary B S D C G Subthreshold C OX WL 0 0 Linear 0 C OX WL/ C OX WL/ Saturation S = D = xwl effective 0.5 S =D B V GS 9 50 First Order Capacitance Summary First Order Capacitance Summary B S D C G Subthreshold C OX WL 0 0 Linear 0 C OX WL/ C OX WL/ Saturation 0 (/3)C OX WL = B S D C G Subthreshold C OX WL 0 0 C OX WL Linear 0 C OX WL/ C OX WL/ C OX WL Saturation 0 (/3)C OX WL 0 (/3)C OX WL 0.5 S D (/3) 0 V DS /(V GS V T ) 5 5 First Order Capacitance Summary Capacitance Roundup B S D C G! C GS =S +C GSO Subthreshold C OX WL 0 0 C OX WL C OX WL+C O! C GD =D +C GDO Linear 0 C OX WL/ C OX WL/ C OX WL C OX WL+C O Saturation 0 (/3)C OX WL 0 (/3)C OX WL (/3)C OX WL +C O! C GB =B! C SB =C diff! C DB =C diff = x = C GSO = C GDO intrinsic extrinsic
10 Step Response? One Implication Step Response Impact of C GD Voltage peaking!! What does C GD do to the switching response here? " " V out Impact of C GD Big Idea! Capacitance " FromTo every terminal " Voltage dependent 0.5 S =D B V GS 0.5 S D 0 V DS /(V GS V T ) (/3)
11 Admin! HW due Thursday, /6 " Need next week s lectures to complete " Homework posted after class 6
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