Section 12: Intro to Devices


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1 Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey
2 Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon crystal in a twodimensional representation. Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si When an electron breaks loose and becomes a conduction electron, a hole is also created. EE143 Ali Javey
3 Semiconductors, Insulators, and Conductors E c E g=1.1 ev E c Ev E g= 9 ev E v Top of conduction band empty filled E c Si, Semiconductor SiO 2, insulator Conductor Totally filled bands and totally empty bands do not allow current flow. (Just as there is no motion of liquid in a totally filled or totally empty bottle.) Metal conduction band is halffilled. Semiconductors have lower E G s than insulators and can be doped EE143 Ali Javey
4 Dopants in Silicon Si Si Si Si Si Si Si As Si Si B Si Si Si Si Si Si Si As, a Group V element, introduces conduction electrons and creates Ntype silicon, and is called a donor. B, a Group III element, introduces holes and creates Ptype silicon, and is called an acceptor. EE143 Ali Javey
5 Types of charges in semiconductors Hole Electron Mobile Charge Carriers they contribute to current flow with electric field is applied. Ionized Donor Ionized Acceptor Immobile Charges they DO NOT contribute to current flow with electric field is applied. However, they affect the local electric field EE143 Ali Javey
6 Fermi Function The Probability of an Energy State Being Occupied by an Electron f ( E) = ( E E ) / kt E 1+ e 1 f E f is called the Fermi energy or the Fermi level. Boltzmann approximation: f ( E E ) kt f ( E) e E E f >> kt E f E f E f + 3kT + 2kT E f + kt ( E E f ) kt f ( E) e f ( E ) kt E ( E) 1 e f E E f << kt E f E f kt E f 2kT E f 3kT ( E f E ) kt f ( E) 1 e f(e) EE143 Ali Javey
7 Electron and Hole Concentrations n = N c e ( E E F C ) / kt N c is called the effective density of states. p = N v e ( E E V F ) / kt N v is called the effective density of states of the valence band. Remember: the closer E f moves up to E c, the larger n is; the closer E f moves down to E v, the larger p is. For Si, N c = cm 3 and N v = cm 3. EE143 Ali Javey
8 Shifting the Fermi Level EE143 Ali Javey
9 General Effects of Doping on n and p I. N N >> n (i.e., Ntype) d a i n p = N d N a = n 2 i n If N d >> N a, n = Nd and p = 2 n i N d II. N N >> a d n i (i.e., Ptype) p n = = N a N n 2 i p d If N >>, a N d p = Na and n = 2 n i N a EE143 Ali Javey
10 When an electric field is applied to a semiconductor, mobile carriers will be accelerated by the electrostatic force. This force superimposes on the random thermal motion of carriers: E =0 E.g. Electrons drift in the direction opposite to the Efield Current flows Average drift velocity = v = μ E 5 1 electron Carrier Drift EE143 Ali Javey Carrier mobility 2 E 1 electron
11 Carrier Mobility Mobile carriers are always in random thermal motion. If no electric field is applied, the average current in any direction is zero. Mobility is reduced by 1) collisions with the vibrating atoms phonon scattering   2) deflection by ionized impurity atoms Coulombic scattering  B  As+ Si EE143 Ali Javey
12 Total Mobility 1600 Mobility (cm 2 V 1 s 1 ) Electrons Holes 1 = τ 1 = μ τ 1 + phonon 1 μ phonon + τ 1 impurity 1 μ impurity E14 1E15 1E16 1E17 1E18 1E19 1E20 Total Impurity N Concenration (atoms cm 3 a + N d (cm 3 ) ) EE143 Ali Javey
13 Conductivity and Resistivity J p,drift = qpv = qpμ p J n,drift = qnv = qnμ n J drift = J n,drift + J p,drift = σ =(qnμ n +qpμ p ) conductivity of a semiconductor is σ = qnμ n + qpμ p Resistivity, ρ = 1/ σ EE143 Ali Javey
14 Relationship between Resistivity and Dopant Density DOPANT DENSITY cm 3 Ntype Ptype RESISTIVITY (Ω cm) ρ = 1/σ EE143 Ali Javey
15 W I + L V Material with resistivity ρ _ R s is the resistance when W = L R s Sheet Resistance t ρ t R s value for a given conductive layer (e.g. doped Si, metals) in IC or MEMS technology is used for design and layout of resistors for estimating values of parasitic resistance in a device or circuit R EE143 Ali Javey L = ρ Wt = R s L W (in ohms/square) if ρ is independent of depth x
16 Diffusion Current Particles diffuse from higher concentration to lower concentration locations. EE143 Ali Javey
17 J n, diffusion = qd Diffusion Current n dn dx J p, diffusion = qd p dp dx D is called the diffusion constant. Signs explained: n p x x EE143 Ali Javey
18 Generation/Recombination Processes Recombination continues until excess carriers = 0. Time constant of decay is called recombination lifetime EE143 Ali Javey
19 PN Junctions Donors Ntype Ptype I + V I V N P Reverse bias Forward bias diode symbol A PN junction is present in almost every semiconductor device. EE143 Ali Javey
20 Energy Band Diagram and Depletion Layer Nregion Pregion (a) E f E c (b) E c E f E v (c) E v E c E f E v n 0 and p 0 in the depletion layer (d) Neutral Nregion Depletion layer Neutral Pregion E c E f E v φ bi = kt q ln N d 2 i n N a EE143 Ali Javey
21 Qualitative Electrostatics Band diagram Built inpotential From ε=dv/dx EE143 Ali Javey
22 Effect of Bias on Electrostatics EE143 Ali Javey
23 Current Flow  Qualitative EE143 Ali Javey
24 PN Diode IV Characteristics I = qv kt I0( e 1) I 0 = Aqn 2 i L D p p N d + Dn L N n a I I + r = 0 A qnw i τ dep dep EE143 Ali Javey
25 Solar Cells light N short circuit P I sc I Dark IV Eq.(4.9.4) V V E c E v + (a) Solar Cell IV Eq.(4.12.1) Maximum I sc poweroutput (b)
26 pin Photodiodes Only electronhole pairs generated in depletion region (or near depletion region) contribute to current Only light absorbed in depletion region contributes to generation Stretch depletion region Can also operate near avalanche to amplify signal
27 Light Emitting Diodes (LEDs) LEDs are typically made of compound semiconductors Why not Si
28 MOS Capacitors MOS: MetalOxideSemiconductor V g metal gate V g gate SiO 2 N + SiO 2 N + Si body Pbody MOS capacitor MOS transistor EE143 Ali Javey
29 Ideal MOS Capacitor Oxide has zero charge, and no current can pass through it. No charge centers are present in the oxide or at the oxidesemiconductor interface. Semiconductor is uniformly doped Φ M = Φ S = χ + (E C E F ) FB
30 Ideal MOS Capacitor At Equilibrium:
31 Ideal MOS Capacitor Under Bias Let us ground the semiconductor and start applying different voltages, V G, to the gate V G can be positive, negative or zero with respect to the semiconductor E F,metal E F,semiconductor = qv G Since oxide has no charge (it s an insulator with no available carriers or dopants), d E oxide / dx = ρ/ε = 0; meaning that the Efield inside the oxide is constant.
32 Inversion condition If we continue to increase the positive gate voltage, the bands at the semiconductor bends more strongly. At sufficiently high voltage, E i can be below E F indicating large concentration of electrons in the conduction band. We say the material near the surface is inverted. The inverted layer is not gotten by chemical doping, but by applying Efield. Where did we get the electrons from? When E i (surface) E i (bulk) = 2 [E F E i (bulk)], the condition is start of inversion, and the voltage V G applied to gate is called V T (threshold voltage). For V G > V T, the Si surface is inverted.
33
34 Ideal MOS Capacitor ntype Si
35
36 Electrostatic potential, φ(x) Define a new term, φ(x) taken to be the potential inside the semiconductor at a given point x. [The symbol φ instead of V used in MOS work to avoid confusion with externally applied voltage, V] 1 φ( x) = [ Ei (bulk) Ei q ( x)] Potential at any point x φ S = 1 q [ E i (bulk) E i (surface)] Surface potential φ F = 1 q [ E i (bulk) E F ] φ F related to doping concentration φ F > 0 means ptype φ F < 0 means ntype
37 Electrostatic potential φ S is positive if the bands bend\.? φ S = 2φ F at the depletioninversion transition point (threshold voltage)
38 Charge Density  Accumulation ptype silicon accumulation condition V G < 0 M O S psi The accumulation charges in the semiconductor are., and appear close to the surface and falloff rapidly as x increases. One can assume that the free carrier concentration at the oxidesemiconductor interface is a δfunction. Accumulation of holes x Charge on metal = Q M Charge on semiconductor = (charge on metal) Q Accumulation = Q M
39 Charge Density  Depletion ptype Si, depletion condition The depletion charges in Si are immobile ions  results in depletion layer similar to that in pn junction or Schottky diode. V G > 0 M O S psi q N A A W = Q M ( ) (+) If surface potential is φ s, then the depletion layer width W will be Q M w Depletion of holes W = 2ε qn Si A φ S Does this equation look familiar?
40 Charge Density  Inversion ptype Si, strong inversion Once inversion charges appear, they remain close to the surface since they are.. Any additional voltage to the gate results in extra Q M in gate and get compensated by extra inversion electrons in semiconductor. V G >>0 Q M M O S w psi Depletion of holes Inversion electrons: δfunctionlike So, the depletion width does not change during inversion. Electrons appear as δ function near the surface. Maximum depletion layer width W = W T
41 MOS CV characteristics The measured MOS capacitance (called gate capacitance) varies with the applied gate voltage A very powerful diagnostic tool for identifying threshold voltage, oxide thickness, substrate doping concentration, and flat band voltage. It also tells you how close to an ideal MOSC your structure is. Measurement of CV characteristics Apply any dc bias, and superimpose a small (15 mv) ac signal (typically 1 khz 1 MHz)
42 CV: under accumulation Consider ptype Si under accumulation. V G < 0 M O S psi V G < 0. Looks similar to parallel plate capacitor. Accumulation of holes C G = C ox where C ox = (ε ox A) / x ox x C G is constant as a function of V G
43 CV: under depletion Depletion condition: V G > 0 V G > 0 M O S ptype Si C G is C ox in series with C s where C s can be defined as semiconductor capacitance Q M C ox W C s Depletion of holes C ox = ε ox A / x ox C s = ε Si A / W C G = C ox C s / (C ox + C S ) 2ε W = qn Si A φ where φ s is surface potential s C G decreases with increasing V G
44 CV: under inversion (high frequency) V G = V T and V G > V T Inversion condition φ s = 2 φ F W = W 2ε Si T = 2 q NA At high frequency, inversion electrons are not able to respond to ac voltage. C ox = ε ox A / x ox φ C s = ε Si A / W T C G (ω )= C ox C s / (C ox + C S ) F V G >>0 Q M M O S W psi Inversion electrons δ function Depletion of holes C ox C s C G will be constant for V G V T
45 CV: under inversion (low frequency) At low frequency, the inversion electrons will be able to respond to the ac voltage. So, the gate capacitance will be equal to the oxide capacitance (similar to a parallel plate capacitance). C G (ω 0) = C ox = ε ox A / x ox C ox C low frequency high frequency V fb V t accumulation depletion inversion V g Ideal MOSC (ptype Si) C G increases for V G V T until it reaches C ox
46 The First Transistor
47 1956 Physics Nobel Prize
48 Invention of the FieldEffect Transistor In 1935, a British patent was issued to Oskar Heil. A working MOSFET was not demonstrated until 1955.
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50 Today s MOSFET Technology Gate oxides as thin as 1.2 nm can be manufactured reproducibly. Large tunneling current through the oxide limits oxidethickness reduction.
51 Introduction to the MOSFET Basic MOSFET structure and IV characteristics
52 Introduction to the MOSFET Two ways of representing a MOSFET:
53
54 Complementary MOSFETs (CMOS) NFET PFET When V g = V dd, the NFET is on and the PFET is off. When V g = 0, the PFET is on and the NFET is off.
55 Qualitative discussion: nmosfet V G > V T ; V DS 0 I D increases with V DS V G > V T ; V DS small, > 0 I D increases with V DS, but rate of increase decreases. V G > V T ; V DS pinchoff I D reaches a saturation value, I D,sat The V DS value is called V DS,sat V G > V T ; V DS > V DS,sat I D does not increase further, saturation region.
56 Threshold voltage for NMOS and PMOS When V G = V T, φ s = 2 φ F ; we get expression for V T. V ε 2q N 2 φ Si A T = φf + xox 2 εox εsi F Ideal nchannel (psilicon) device both terms positive V T ε 2 = 2φ + Si q ND F xox 2φF εox εsi ε Si / ε ox = = 11.9 / Ideal pchannel (nsilicon) device both terms negative 1 φf = [ Ei (bulk) EF] q φ F > 0 means ptype φ F < 0 means ntype
57 How to Measure the V T of a MOSFET I ds V ds = 10mV V t V t is measured by extrapolating the I ds versus V gs (at low V ds ) curve to I ds = 0. V gs I dsat W = Coxe( Vgs Vt ) μnsv L ds V gs V t
58 Quantitative I D V DS Relationships 1 st attempt I D = Zμ L n C ox ( V V ) G T Square Law V DS 2 DS V 2 < V DS < ; DS, sat V G > VT 0 V I D will increase as V DS is increased, but when V G V DS = V T, pinchoff occurs, and current saturates when V DS is increased further. This value of V DS is called V DS,sat. i.e., V DS,sat = V G V T and the current when V DS = V DS,sat is called I DS,sat. I D,sat Z μc 2 L = ox G T D V DS, sat ( V V ) 2 V > ; V G > VT Here, C ox is the oxide capacitance per unit area, C ox = ε ox / x ox
59 I D V DS characteristics expected from a long channel (ΔL << L) MOSFET (nchannel), for various values of V G
60 Nchannel MOSFET Layout (Top View) 4 lithography steps are required: 1. active area 2. gate electrode 3. contacts 4. metal interconnects EE143 Ali Javey
61 Simple NMOS Process Flow 1) Thermal oxidation (~10 nm pad oxide ) 2) Siliconnitride (Si 3 N 4 ) deposition by CVD (~40nm) 3) Activearea definition (lithography & etch) 4) Boron ion implantation ( channel stop implant) EE143 Ali Javey
62 5) Thermal oxidation to grow oxide in field regions 6) Si 3 N 4 & pad oxide removal 7) Thermal oxidation ( gate oxide ) 8) PolySi deposition by CVD 9) PolySi gateelectrode patterning (litho. & etch) Simple NMOS Process Flow 10) P or As ion implantation to form n+ source and drain regions Top view of masks EE143 Ali Javey
63 Simple NMOS Process Flow 11) SiO 2 CVD Top view of masks 12) Contact definition (litho. & etch) 13) Al deposition by sputtering 14) Al patterning by litho. & etch to form interconnects EE143 Ali Javey
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