EE5311- Digital IC Design

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1 EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 1/41

2 Learning Objectives Explain short channel effects(sce) like Drain Induced Barrier Lowering, Gate Induced Drain Leakage, Sub-threshold leakage, Channel length modulation Derive the equation for ON current of a CMOS transistor with first order SC Estimate various capacitance values for a transistor Estimate the equivalent ON resistance of a transistor Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 2/41

3 Outline Silicon and Doping P-N Junction CMOS Transistor Threshold Voltage ON Current (ION ) Channel length modulation Velocity saturation Sub-threshold leakage Drain Induced Barrier Leakage Gate Induced Drain leakage (Reverse) Short Channel Effect Other leakage mechanisms Capacitance Resistance Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 3/41

4 Silicon and Doping Si Si Si Si Si Si Unbound Electron Si Missing Electron Si P Si Si B Si Si Si N Type Donor P Type Acceptor n i - Intrinsic electron/ hole concentration Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 4/41

5 Device Physics Abstraction 1. Law of Mass Action - Product of concentrations remains constant Where np = n 2 i n/p = Electron/ hole concentration after doping ni = Intrinsic electron/ hole concentration 2. Maxwell Boltzmann Equation - Where n 1 n 2 = e Ψ12 kt/q kt/q - Thermal voltage = 300K n1,n 2 - Charge concentration across a potential ψ 12 Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 5/41

6 PN Junction P W n W p Figure: PN Junction Diode W n N D = W p N A Conservation of charge Note: N D N A = W p W n Current is due to diffusion of minority carriers Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 6/41

7 NMOS Transistor V S V G V D W L e T ox P V B Figure: NMOS transistor V GS < 0 - Accumulation (Surface becomes more P type than bulk) 0 V GS < V TH - Depletion (Surface is less P type than bulk) V GS V TH - Inversion (Surface is more N than the bulk is P) Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 7/41

8 Threshold Voltage B S G D Ψ S n Bulk e = n2 i NA n Surface e = N A P Figure: G = V TH - Channel is as N-type as the body is P-type Ψ S = 2 kt q ln(n A n i ) V GB = ψ OX +ψ S Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 8/41

9 Threshold Voltage W D = Depletion width and Q D = Depletion charge per unit area 2ǫ si ψ s W D = qn A Q D = qn A W D = 2qN A ψ s ψ OX = (Q D +Q I ) C ox C ox = ǫ ox t ox V TH = ψ S Q D C ox Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 9/41

10 Threshold Voltage V B 0 Body effect alters depletion region charge Q D = 2qN A ǫ Si Ψ S +V SB V TH = V TH0 +γ( Ψ S +V SB (Ψ S ) ) Technolopgy parameters V TH0 - Threshold voltage without body effect γ - Body effect coefficient Ψ S - Positive (Negative) for NMOS (PMOS) transistors Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 10/41

11 NMOS Transistor B S V GS V DS I D V x L x P Figure: NMOS Transistor V GS 0 - OFF V GS > V TH and V DS < V GS V TH - Linear V GS > V TH and V DS > V GS V TH - Saturation Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 11/41

12 NMOS - ON Current - Linear Region B S V GS V DS I D V x L x P Figure: NMOS Transistor Q i (x) = C OX [V GS V x V TH ] C OX = ǫ OX t OX I D = v n Q i (x)w Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 12/41

13 NMOS - ON Current - Linear Region v n = µ n E(x) Substituting we get v n = µ n dv x dx L 0 I D dx = dv x I D = C OX [V GS V x V TH ]Wµ n dx VDS 0 I D = k n C OX [V GS V x V TH ]Wµ n dv x W L [(V GS V TH )V DS V2 DS 2 ] Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 13/41

14 NMOS - ON Current - Saturation B S V GS V DS I D V P L x P Figure: NMOS Transistor under pinch off voltage (V P ) condition I D = k n W 2 L [(V GS V TH ) 2 ] Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 14/41

15 Short Channel Effects B S V GS L V DS I D L V DS = V DD V DS = 0 P V DS << V DD Figure: NMOS Transistor with Short Channel Effects Drain is very close to the source (L is very small) The depletion regions in the drain and source are comparable to the channel length Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 15/41

16 Channel Length Modulation B S VGS L VDS ID L VDS = VDD VDS = 0 P VDS << VDD Figure: NMOS Transistor with Short Channel Effects I D = k n W 2 L L [(V GS V TH ) 2 ] I D = k n W 2 L [(V GS V TH ) 2 ](1+ L L ) I D = k n W 2 L [(V GS V TH ) 2 ](1+λV DS ) Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 16/41

17 Velocity Saturation v n = µ n E Lat Not entirely correct - Velocity does not linearly increase with lateral field for ever It saturates beyond a critical field E Crit Electrons encounter more collisions and hence don t pick up speed Maximum velocity of electrons/ holes = 10 5 m/s Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 17/41

18 Velocity Saturation 0.8 v(m/s)( 10 5 ) E(V/µm) v = µe 1+ E E C v sat if E E C if E > E C Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 18/41

19 Velocity Saturation- Simplified Velocity: VDS Saturation : v = { µe if E E C v sat = µe C if E > E C V DS SAT = L E C = Lv SAT µ Velocity Saturated Drain Current: I DS SAT = µ n C OX W L I DS SAT = I DS (V DS = V DS SAT ( ) (V GS V TH )V DS SAT V2 DS SAT 2 Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 19/41

20 Unified Current Model Useful to combine all effects into one equation Voltage values determine the governing equations { 0 VGS < V TH I DS = ( ) k W (V L GS V TH )V min V2 min )(1+λV 2 DS V GS > V TH Where V min = min(v DS,(V GS V TH ),V DS SAT )...NMOS V min = max(v DS,(V GS V TH ),V DS SAT )...PMOS V TH = V TH0 +γ( V SB +Ψ S Ψ S ) (V TH0,k,V DSAT,γ,λ) - Technology parameters Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 20/41

21 Sub-threshold Leakage B S VGS = 0 VDS IOFF Thin Base Emitter Collector P Figure: NMOS Transistor Sub-Threshold Leakage In a short channel transistor, the thin channel acts like a thin base of a BJT. Diffusion current flows even when V GS = 0. Exponential dependence on V GS I OFF = I S e V GS V TH nkt/q ( ) 1 e V DS kt/q (1+λV DS ) Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 21/41

22 Sub-threshold Slope ma I DS Log GIDL na IOFF Linear S = V GS 1 d(log 10 (I OFF )) dv GS S = n kt q ln(10) Ideal transistor n = 1, S min = 60mV/decade Actual transistors n 1.5 and hence S = 90mV/decade Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 22/41

23 Gate Induced Drain Leakage (GIDL) B S VGS << 0 VDS = VDD P+ IGIDL P Figure: NMOS Transistor with Halo Implant Negative V GS exponentially reduces sub-threshold leakage But beyond a point GIDL kicks in Surface is in deep accumulation causing a deeper depletion in the diffusion Tunneling current from drain to substrate Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 23/41

24 Drain Induced Barrier Lowering (DIBL) B S VGS VDS ID L VDS = VDD VDS = 0 P VDS << VDD Figure: NMOS Transistor DIBL Drain controls amount of depletion in the channel Easier for the gate to invert with higher V DS Gate effectively has lesser control Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 24/41

25 Drain Induced Barrier Lowering (DIBL) B S VGS VDS ID L P + P + P Figure: NMOS Transistor with Halo Implant P + halo added near diffusion Depletion layer now goes deeper into the diffusion rather than channel Gate has better control now DIBL = V TH(V DS =V H DD ) V TH(V DS =V L DD ) V H DD VL DD Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 25/41

26 Reverse Short Channel Effect RSCE VTH SCE L Halo implant makes it harder to invert the channel Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 26/41

27 Substrate Leakage B S V GS V DS I SUB LEAK P Reverse biased P junction leakage Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 27/41

28 Gate Leakage tox = 4nm B S VGS VDS Scaling P tox = 1nm B S IGATE P Quantum mechanical tunneling across the gate oxide Use of HfO 2 - HiK dielectric since 45nm technology Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 28/41

29 Capacitance D C gd C db G C gs S C sb B C gb Figure: Capacitance Model Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 29/41

30 Gate Capacitance G C C 0 Accumulation Depletion Inversion V GB B Figure: Capacitance Model C 0 = ǫwl t ox Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 30/41

31 Gate Capacitance Parameter Cutoff Linear Saturation C gb C C gs 0 C 0 /2 (2/3)C 0 C gd 0 C 0 /2 0 C g = C gb +C gs +C gd C 0 C 0 (2/3)C 0 C 0 = ǫ oxwl t ox For all practical purposes C g C 0 Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 31/41

32 Overlap Capacitance Cross Section L x d Ld W Top View Figure: Overlap Capacitance C ov = ǫ oxwx d t ox C G = C 0 +2C ov Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 32/41

33 Diffusion Capacitance W x j D D L S N A Figure: Diffusion Capacitance Bottom plate capacitance Sidewall capacitance Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 33/41

34 Diffusion Capacitance Side Wall W Side Wall N D Source Bottom x j Side Wall L S Channel Substrate N A Figure: Diffusion Capacitance Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 34/41

35 Bottom Plate Diffusion Capacitance W xj D D LS NA C j0 = C Bottom = C j WL S C j0 C j = (1+V SB /φ 0 ) m ( ǫ siq N A N D )φ N A +N D φ 0 = kt q ln(n AN D ) n 2 i m 0.5 C j is charge per unit area. Similar expressions hold for the drain side (V SB V DB ) as well. Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 35/41

36 Side wall Diffusion Capacitance W x j D D L S N A Figure: Diffusion Capacitance C Side wall = C jswx j (W +2L S ) C jsw = C jswx j C diff = C bottom +C sw = C j L S W +C jsw (W +2L S ) C jsw is capacitance per unit length. Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 36/41

37 Capacitance Summary D G C gd C gs S C db B C gb C sb Figure: NMOS Capacitance C G = C GS +C GD +C GB +2C ov = C OX WL+2C ov C DB = C j L S W +C jsw (W +2L S ) C SB = C j L S W +C jsw (W +2L S ) Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 37/41

38 Resistance V DS (V DD V DD /2) V DD I D R eq = Figure: NMOS Equivalent Resistance R eq = 1 V DD /2 V DD 1 V DD /2 VDD /2 V DD R eq 3V DD 4I DSAT VDD /2 V DD R(V)dV V I DSAT (1+λV) dv ( 1 7 ) 9 λv DD Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 38/41

39 Resistance R eq 3V DD 4I DSAT ( 1 7 ) 9 λv DD I DSAT = k W L ((V DD V TH )V DSAT V2 DSAT 2 Resistance R eq 1 W/L - Doubling W = R eq halves If V DD >> V TH +V DSAT /2, R eq is independent of V DD. Minor dependence due to CLM (λ) As V DD V TH, resistance goes up significantly ) Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 39/41

40 BSIM SPICE Level 1 Model V TH0 γ(v 0.5 ) V DSAT (V) k (µa/v 2 ) λ(v 1 ) NMOS PMOS Table: Parameters of a 0.25µm CMOS process for a minimum length device Calculate the drain current of a PMOS transistor in 0.25µm technology whose W/L = 0.5µ/0.25µ when biased at V GS = 0.6V, V DS = 0.3V and V SB = 0V Repeat the above calculation this time with V DS = 1.1V and V GS = 2V Calculate the threshold voltage of a NMOS device when the body is biased at V SB = 0.11V. Assume that ψ S = 0.25V Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 40/41

41 Capacitance Model C OX C ov C j m j φ b C jsw m jsw φ bsw (ff/µm 2 ) (ff/µm) (ff/µm 2 ) (V ff/µm) (V) NMOS PMOS Table: Capacitance parameters of a 0.25µm CMOS process Calculate variaous capacitances of an NMOS transistor with W/L = 0.36µm/0.24µm in a 0.25µm technology where L D = L S = 0.625µm under zero-bias condition Calculate the equivalent resistance of an NMOS transistor with a W/L = 1 when connected to a V DD = 1.5V Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 41/41

42 References The material presented here is based on the following books/ lecture notes 1. Digital Integrated Circuits Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice Hall India Janakiraman, IITM EE5311- Digital IC Design, Module 1 - The Transistor 42/41

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction