B.Supmonchai June 26, q Introduction of device basic equations. q Introduction of models for manual analysis.

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1 June 26, 2004 oal of this chapter Chapter 2 MO Transistor Theory oonchuay upmonchai Integrated esign Application Research (IAR) Laboratory June 16th, 2004; Revised June 16th, 2005 q Present intuitive understanding of device operation q Introduction of device basic equations q Introduction of models for manual analysis First-Order Model q Analysis of secondary and deep-sub-micron effects q Future trends igital ICs MO Transistor Theory 2 The iode iode - epletion Region Al A io 2 hole diffusion electron diffusion p p n (a) Current flow. Cross-section of pn-junction in an IC process A diode symbol igital ICs MO Transistor Theory 3 A p n One-dimensional representation Mostly occurring as parasitic element in igital ICs n Al Charge ensity Electrical Field Potential -W 1 hole drift electron drift - r x V + W 2 x istance igital ICs MO Transistor Theory 4 y 0 x x (b) Charge density. (c) Electric field. (d) Electrostatic potential igital ICs 1

2 June 26, 2004 iode - Zero ias iode - Forward ias q uild-in (Electrostatic) Potential: current Ê f 0 = f T ln N AN ˆ Á 2 Ë n i f T = Thermal Voltage = kt/q = 26 mv at 300 K (i) n i = Intrinsic carrier concentration ~ 1.5 x cm -3 N A = Acceptor concentration (atoms/cm 3 ) N = onor concentration (atoms/cm 3 ) igital ICs MO Transistor Theory 5 Excess Carriers Excess Carriers iffusion iffusion Typically avoided in igital ICs igital ICs MO Transistor Theory 6 iode - Reverse ias iode Types current iffusion iffusion 0.37p n0 Linear Approximation Exponentially istributed The ominant Operation Mode igital ICs MO Transistor Theory 7 hort-ase iode is the standard in semiconductor devices igital ICs MO Transistor Theory igital ICs 2

3 June 26, 2004 iode Current Models for iode Manual Analysis V + I V + I + V on (typ. 0.7 V) V = iode ias Voltage, I = iode Current igital ICs MO Transistor Theory 9 Ideal iode Model I = I e V f ( T -1) First-order iode Model I s = aturation Current ~ A/mm igital ICs MO Transistor Theory 10 Example: A iode Circuit iode - Junction Capacitance 1: I = I [exp(v /f T ) - 1] 2: I = (V - V )/R Using V (ON) = 0.7 V I = 0.23 ma V = 0.7 V raphic olution I = ma V = V C j = C j 0 ( ) m 1-V f 0 C j0 = Zero-iased Junction Capacitance = f(physical parameters) m = rading Coefficient (0.5 - Abrupt, linear ) igital ICs MO Transistor Theory igital ICs MO Transistor Theory igital ICs 3

4 June 26, 2004 iode - iffusion Capacitance iode witching Time V 1 R src V V 2 t = 0 t = T V src I Excess charge pace charge C d = dq di = t T ª t T I dv dv f T t = mean transit time V ON OFF ON witching Time is strongly determined by how fast the charge can be moved around = average time for a carrier to be transported from the junction to the metallic contact Time igital ICs MO Transistor Theory igital ICs MO Transistor Theory 14 iode - econdary Effects I iode - econdary Effects II Avalanche reakdown Temperature Effects E crit = 2x10 5 V/cm f T µ T I = f(t) Theory: 2X every 5ºC Experiment: 2X every 8ºC -20 reakdown Voltage At Critical Field E crit, carriers crossing the depletion region is accelerated to high velocity such that when they collide with immobile silicon atoms, electron-hole pairs are created igital ICs MO Transistor Theory 15 I increases 6% per ºC (2X every 12 º C) (For fixed I ) V decreases 2mV per ºC igital ICs MO Transistor Theory igital ICs 4

5 June 26, 2004 iode PICE Model PICE iode Model Parameters + I R Neutral Regions + V V I C - - I = I e V nf ( T -1) C j = C j 0 ( ) m + t T I 1-V f 0 n = emission coefficient ( 1) f T e V nf T igital ICs MO Transistor Theory igital ICs MO Transistor Theory 18 What is a MO(FET) Transistor? q Metal-Oxide-emiconductor Field-Effect Transistor (MOFET, or MO, for short) q A Four-terminal device ate controls how much current can flow from the ource to the rain. ody modulates device characteristics and parameters - secondary effect. q A switch! igital ICs MO Transistor Theory 19 MO Transistors - Types and ymbols NMO with ulk Contact NMO epletion igital ICs MO Transistor Theory 20 NMO Enhancement PMO Enhancement The ody terminal, if not shown, is assumed to be connected to the appropriate supply igital ICs 5

6 June 26, 2004 witch Model of NMO Transistor witch Model of PMO Transistor V ate V ate ource (of carriers) rain (of carriers) ource (of carriers) rain (of carriers) Open (off) (ate = 0 ) Closed (on) (ate = 1 ) R on Open (off) (ate = 0 ) Closed (on) (ate = 1 ) R on V < V T V > V T V > V V T V < V V T igital ICs MO Transistor Theory igital ICs MO Transistor Theory 22 Why MO Transistor? q MO performs well as a switch with very few parasitic effects. q Relatively imple manufacturing process (compared to other types of transistor) q High Integration ensity Large and Complex circuits can be created economically. The NMO Transistor Polysilicon Aluminum igital ICs MO Transistor Theory igital ICs MO Transistor Theory igital ICs 6

7 June 26, 2004 The NMO Transistor Cross ection ource n+ W Polysilicon ate L p substrate ulk (ody) ate oxide rain n+ Field-Oxide (io 2 ) p+ stopper n areas have been doped with donor ions (arsenic) of concentration N - electrons are the majority carriers p areas have been doped with acceptor ions (boron) of concentration N A - holes are the majority carriers MO Transistors - ehaviors q tatic ehavior: Threshold Voltage Channel-Length Modulation Velocity aturation ub-threshold Conduction q ynamic (Transient) ehavior: MO tructure Capacitances Channel Capacitances Junction Capacitances ources-rain Parasitic Resistance igital ICs MO Transistor Theory igital ICs MO Transistor Theory 26 Threshold Voltage Concept n channel V + n+ n+ p substrate The value of V where strong inversion occurs is called the threshold voltage, V T igital ICs MO Transistor Theory 27 depletion region Threshold Voltage Components I q Work function difference between the gate and the channel, f C f C = f F (substrate) - f M for metal gate f C = f F (substrate) - f F (gate) for polysilicon gate q ate voltage component to change (invert) the surface potential, 2f F Fermi Potential, f F = f T ln(n A / n i ) f F ~ -0.3 V for p-type silicon substrate igital ICs MO Transistor Theory igital ICs 7

8 V T (V) June 26, 2004 Threshold Voltage Components II q ate voltage component to offset the depletion region charge, Q / C ox ate Oxide Capacitance per unit area, C ox = e ox / t ox epletion region charge, Q = 2qN A e si -2f F -V q Voltage component to offset fixed charges in the gate oxide and in the silicon-oxide surface, Q / C ox q Threshold adjustment by applying the ion implantation into the channel, Q I / C ox igital ICs MO Transistor Theory 29 The Threshold Voltage V T = f C - 2f F - Q C ox - Q C ox - Q I C ox V T = V T 0 + g ( -2f F + V - -2f F ) V T 0 = V T V = 0 g = 2q N Ae si C ox ody-effect coefficient igital ICs MO Transistor Theory 30 The ody Effect - Empirically V (V) V normally positive for n-channel devices with the body tied to ground A negative bias causes V T to increase from 0.45V to 0.85V igital ICs MO Transistor Theory 31 V Transistor in Resistive (Linear) Mode Assume V > V T n+ - V(x) + n+ x The current is a linear function of both V and V igital ICs MO Transistor Theory 32 V I igital ICs 8

9 June 26, 2004 Transistor in aturation I-V Relations: Long-Channel evice Assume V > V T V V > V - V T Quadratic Relationship n+ - V -V T + n+ x Pinch-off The current remains constant (saturates) igital ICs MO Transistor Theory 33 Linear Relationship Effective Length of the conductive channel is inversely proportional to V igital ICs MO Transistor Theory 34 Long-Channel I-V Plot (NMO) cut-off I (A) X V = V - V T Linear V = 2.5V V = 2.0V aturation V = 1.5V V = 1.0V V (V) NMO transistor, 0.25um, L d = 10um, W/L = 1.5, V = 2.5V, V T = 0.4V igital ICs MO Transistor Theory 35 Quadratic dependence Velocity aturation u n (m /s ) Constant velocity Constant mobility (slope = µ) Ï m n x Ô for x x u = Ì c 1+ x x c Ó Ô u sat for x > x c u sat = 10 5 x c = 1.5 x (V/µm) igital ICs MO Transistor Theory igital ICs 9

10 June 26, 2004 hort-channel evices I-V Relation: hort-channel evices I V = V Long-channel device hort-channel device q Linear Region: V V V T I = k(v ) k n W/L [(V V T )V V 2 /2] where k(v) = 1/(1 + (V/x c L)) is a measure of the degree of velocity saturation V AT Extended saturation V - V T V For an NMO device with L of.25mm, only a couple of volts between and are needed to reach velocity saturation igital ICs MO Transistor Theory 37 q aturation Mode: V = V AT V V T I AT = k(v AT ) k n W/L [(V V T )V AT V AT2 /2] where V AT = (V V T )k(v V T ) igital ICs MO Transistor Theory 38 hort-channel IV Plots (NMO) I (A) X Linear Early Velocity aturation aturation V = 2.5V V = 2.0V V = 1.5V V = 1.0V V (V) NMO transistor, 0.25um, L d = 0.25um, W/L = 1.5, V = 2.5V, V T = 0.4V igital ICs MO Transistor Theory 39 Linear dependence I (A) Velocity aturation Effects X 10-4 I -V Characteristics long-channel quadratic (for V = 2.5V, W/L = 1.5) short-channel linear V (V) q hort-channel evices tend to operate in saturation conditions more often than the longchannel devices. q Velocity-saturation causes the short-channel device to saturate at substantially smaller values of V resulting in a substantial drop in current drive igital ICs MO Transistor Theory igital ICs 10

11 June 26, 2004 A PMO Transistor ub-threshold Conduction I (A) x 10-4 V = -1.0V V = -1.5V V = -2.0V V = -2.5V Assume all voltage Variables negative! V (V) PMO transistor, 0.25um, L d = 0.25um, W/L = 1.5, V = -2.5V, V T = -0.4V igital ICs MO Transistor Theory 41 ) (A ) (I ln I (A) Quadratic region 90 mv/decade Linear region ubthreshold exponential region V T V (V) Ê = n kt ˆ Á ln 10 Ë q ( ) Charges are leaking through the devices, of which the rate is determined by the slope factor in the subthreshold region igital ICs MO Transistor Theory 42 A Unified Model for Manual analysis imple Model versus PICE For NMO, all five parameters (V TO, g, V AT, k, l) are positive. For PMO, they are negative. I (A) -4 x Linear V =V AT PICE Velocity aturated Model V =V T aturated V AT =V T V (V) igital ICs MO Transistor Theory igital ICs MO Transistor Theory igital ICs 11

12 June 26, 2004 Transistor Model for Manual analysis The Transistor Modeled as a witch Parameters for manual model of generic 0.25 um CMO process (Minimum length device) q q NMO PMO V T0 (V) g(v 0.5 ) V AT (V) k (A/V 2 ) 115 x x 10-6 l(v -1 ) Caution! Try to extrapolate the behavior of the device other than W and L given in the table can lead to sizable errors. igital Circuits usually use Minimum Length devices R eq (Ohm) x V V T R o n V (V) (for V = V, V = V ÆV /2) V (V) NMO(kW) PMO (kw) Modeled as a switch with infinite off resistance and a finite on resistance, R on l Resistance inversely proportional to W/L (doubling W halves R on ) l For V >>V T +V AT /2, R on independent of V l Once V approaches V T, R on increases dramatically R on (for W/L = 1) For larger devices divide R eq by W/L igital ICs MO Transistor Theory igital ICs MO Transistor Theory 46 ynamic ehavior of MO Transistor MO Transistor Capacitances C C C C C igital ICs MO Transistor Theory igital ICs MO Transistor Theory igital ICs 12

13 June 26, 2004 Overlap Capacitances ate-channel Capacitances Polysilicon gate ource n + x d x d rain W n + C ox = e ox t ox (F/m 2 ) Cut-off Resistive aturation L d Top view ate-bulk overlap C ol = C ox x d W = C o W ate oxide C gso = C gdo = C ol t ox n + L n + Cross section *C fringe = (2e ox /p) ln (1+T poly /t ox ) Most important regions in digital design: saturation and cut-off igital ICs MO Transistor Theory igital ICs MO Transistor Theory 50 Variation of ate-channel Capacitances iffusion Capacitances WLC ox WLC ox 2 C C V T C C C C = C C V WLC ox WLC ox 2 C C C C C C 0 V /(V -V T ) 1 2WLC ox 3 io 2 p ate 4 3 L W n+ x j ubstrate Capacitance as a function of V (with V = 0) Capacitance as a function of the degree of saturation C diff = C ottom + C idewall = C 1 + (C 2 + C 3 + C 4 + C 5 ) C diff = C j L W + C jsw (2L + W ) igital ICs MO Transistor Theory igital ICs MO Transistor Theory igital ICs 13

14 June 26, 2004 Junction Capacitance: Recap Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest igital ICs MO Transistor Theory igital ICs MO Transistor Theory 54 MO Transistor Capacitance: ummary ate Capacitances in 0.25 mm CMO process Capacitance parameters of NMO and PMO transistors in 0.25 mm CMO process. C = C gs + C gso C = C gd + C gdo ource C = C gb C = C diff rain C = C diff q For an NMO transistor with t ox = 6 nm, L = 0.24 mm, W = 0.36 mm, L = L = mm Total ate Capacitance C = C g + 2C ol = 0.7 ff C = C = 0.89 ff ody igital ICs MO Transistor Theory igital ICs MO Transistor Theory igital ICs 14

15 June 26, 2004 Parasitic Resistance The M MO Transistor V,eff R R Polysilicon gate L rain contact q econdary Effects become more pronounce in the deep-submicron transistor. Threshold Variations Hot Carrier Effects W CMO Latchup R, = L, W R sq + R C R sq = heet Resistance per square ( ohms/sq.) R C = Contact Resistance rain Careless Layout may lead to resistances that severely degrade device performance igital ICs MO Transistor Theory 57 q esigning the circuits with all secondary effects taken into account is intractable and results can be obscure. q Analyze with first-order model, then readjust the model with the help of CA simulation tools igital ICs MO Transistor Theory 58 Threshold Variations Hot Carrier Effects V T Long-channel threshold V T Low V threshold q Electrons become hot, i.e. reaching a critical high level of energy, under intense electric field which occurs when the channel is short. E crit 10 4 V/m hort-channel threshold q Hot electrons can leave the silicon and tunnel into the gate oxide. Threshold as a function of the length (for low V ) L V rain-induced barrier lowering or IL (for low L) q Electrons trap in the gate oxide increase NMO threshold and decrease PMO threshold. q Hot electron phenomenon leads to a long-term reliability problem igital ICs MO Transistor Theory igital ICs MO Transistor Theory igital ICs 15

16 June 26, 2004 CMO Latch-up Future Perspectives V V p + n + n + p + p + n + R nwell p-source n-well R nwell R psubs p-substrate n-source R psubs (a) Origin of latchup (b) Equivalent circuit q q q Latchup causes positive feedback of the current until the circuit fails or burns out. To avoid Latchup, R nwell and R psubs should be minimized. evices carrying a lot of current need uard Rings igital ICs MO Transistor Theory nm FINFET MO transistor igital ICs MO Transistor Theory igital ICs 16