# Lecture 5: CMOS Transistor Theory

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1 Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design

2 Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance Nonideal Transistor Behavior High Field Effects Channel Length Modulation Threshold Voltage Effects Leakage Process and Environmental Variations q Reading CMOS Transistor Theory CMOS VLSI Design 2

3 Introduction q So far, we have treated transistors as ideal switches q An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships q Transistor gate, source, drain all have capacitance I = C (ΔV/Δt) -> Δt = (C/I) ΔV Capacitance and current determine speed CMOS Transistor Theory CMOS VLSI Design 3

4 MOS Capacitor q q Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion (a) V g < polysilicon gate silicon dioxide insulator p-type body 0 < V g < V t depletion region + - (b) V g > V t + - inversion region depletion region (c) CMOS Transistor Theory CMOS VLSI Design 4

5 Terminal Voltages q Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d V gs - + V g + V gd - q q q V ds = V d V s = V gs - V V gd s Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation - V + ds V d CMOS Transistor Theory CMOS VLSI Design 5

6 nmos Cutoff q No channel q I ds 0 V gs = g + - V gd s d n+ n+ p-type body b CMOS Transistor Theory CMOS VLSI Design 6

7 nmos Linear q Channel forms q Current flows from d to s e - from s to d q I ds increases with V ds q Similar to linear resistor V gs > V t + - s g + - V gd = V gs n+ n+ V ds = 0 p-type body b d V gs > V t + - g + - V gs > V gd > V t s d I ds n+ n+ p-type body b 0 < V ds < V gs -V t CMOS Transistor Theory CMOS VLSI Design 7

8 nmos Saturation q Channel pinches off q I ds independent of V ds q We say current saturates q Similar to current source V gs > V t + - g + - V gd < V t s d I ds n+ n+ p-type body b V ds > V gs -V t CMOS Transistor Theory CMOS VLSI Design 8

9 I-V Characteristics q In Linear region, I ds depends on How much charge is in the channel How fast the charge is moving CMOS Transistor Theory CMOS VLSI Design 9

10 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversions Gate oxide channel q Q channel = CV q C = C g = ε ox WL/t ox = C ox WL q V = V gc V t = (V gs V ds /2) V t gate t ox L n+ n+ p-type body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain - - channel n+ - + n+ V s V ds p-type body V d CMOS Transistor Theory CMOS VLSI Design 10

11 Carrier velocity q Charge is carried by e- q Electrons are propelled by the lateral electric field between source and drain E = V ds /L q Carrier velocity v proportional to lateral E-field v = µe µ called mobility q Time for carrier to cross channel: t = L / v CMOS Transistor Theory CMOS VLSI Design 11

12 nmos Linear I-V q Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross CMOS Transistor Theory CMOS VLSI Design 12

13 nmos Saturation I-V q If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t q Now drain voltage no longer increases current CMOS Transistor Theory CMOS VLSI Design 13

14 nmos I-V Summary q Shockley 1 st order transistor models CMOS Transistor Theory CMOS VLSI Design 14

15 Example q Use 0.6 µm process From AMI Semiconductor t ox = 100 Å µ = 350 cm 2 /V*s V t = 0.7 V q Plot I ds vs. V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 λ 14 W W W β = µcox = ( 350) 120 µa/v L 8 = L L I ds (ma) V ds V gs = 5 V gs = 4 V gs = 3 V gs = 2 V gs = 1 CMOS Transistor Theory CMOS VLSI Design 15

16 pmos I-V q All dopings and voltages are inverted for pmos Source is the more positive terminal q Mobility µ p is determined by holes Typically 2-3x lower than that of electrons µ n 120 cm 2 /V s in AMI 0.6 µm process q Thus pmos must be wider to provide same current In this class, assume µ n / µ p = 2 I ds (ma) V gs = -4 V gs = -3 V gs = -2 V gs = V ds V gs = -1 CMOS Transistor Theory CMOS VLSI Design 16

17 Capacitance q Any two conductors separated by an insulator have capacitance q Gate to channel capacitor is very important Creates channel charge necessary for operation q Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion CMOS Transistor Theory CMOS VLSI Design 17

18 Gate Capacitance q Approximate channel as connected to source q C gs = ε ox WL/t ox = C ox WL = C permicron W q C permicron is typically about 2 ff/µm polysilicon gate W t ox L n+ n+ p-type body SiO2 gate oxide (good insulator, ε ox = 3.9ε 0 ) CMOS Transistor Theory CMOS VLSI Design 18

19 Diffusion Capacitance q C sb, C db q Undesirable, called parasitic capacitance q Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½ C g for uncontacted Varies with process CMOS Transistor Theory CMOS VLSI Design 19

20 Ideal Transistor I-V q Shockley long-channel transistor models 0 Vgs < V V I = β V V ds V V V 2 < β ( V V ) 2 V > V 2 ds gs t ds ds dsat gs t ds dsat t cutoff linear saturation 20

21 Ideal vs. Simulated nmos I-V Plot q 65 nm IBM process, V DD = 1.0 V I ds (ma) Simulated Ideal V gs = 1.0 Velocity saturation & Mobility degradation: I on lower than ideal model predicts I on = 747 Channel length modulation: V gs = V ds = V DD Saturation current increases with V ds V gs = Velocity saturation & Mobility degradation: Saturation current increases less than quadratically with V gs V gs = 0.8 V gs = V gs = 0.6 V gs = 0.6 V gs = V ds 21

22 ON and OFF Current q I on = I V gs = V ds = V DD Saturation Ids (ma) Ion = 747 Vgs = Vds = VDD Vgs = 1.0 Vgs = Vgs = Vgs = Vds q I off = I V gs = 0, V ds = V DD Cutoff 22

23 Electric Fields Effects q Vertical electric field: E vert = V gs / t ox Attracts carriers into channel Long channel: Q channel E vert q Lateral electric field: E lat = V ds / L Accelerates carriers from drain to source Long channel: v = µe lat 23

24 Coffee Analogy q Tired student runs from ECE425 lab to ECE cafe q Freshmen are pouring out of the ECE 120 lecture hall q V ds is how long you have been up Your velocity = fatigue mobility q V gs is a wind blowing you against the glass (SiO 2 ) wall q At high V gs, you are buffeted against the wall Mobility degradation q At high V ds, you scatter off freshmen, fall down, get up Velocity saturation Don t confuse this with the saturation region 24

25 Mobility Degradation q High E vert effectively reduces mobility Collisions with oxide interface 25

26 Velocity Saturation q At high E lat, carrier velocity rolls off Carriers scatter off atoms in silicon lattice Velocity reaches v sat Electrons: 10 7 cm/s Holes: 8 x 10 6 cm/s Better model 26

27 Threshold Voltage Effects q V t is V gs for which the channel starts to invert q Ideal models assumed V t is constant q Really depends (weakly) on almost everything else: Body voltage: Body Effect Drain voltage: Drain-Induced Barrier Lowering Channel length: Short Channel Effect 27

28 Body Effect q q q q Body is a fourth transistor terminal V sb affects the charge required to invert the channel Increasing V s or decreasing V b increases V t ( ) V = V + γ φ + V φ t t0 s sb s φ s = surface potential at threshold N A φ s = 2vT ln n i Depends on doping level N A And intrinsic carrier concentration n i γ = body effect coefficient γ t ox = 2qεsiN A = εox 2qε N C si ox A 28

29 Body Effect Cont. q For small source-to-body voltage, treat as linear 29

30 DIBL q Electric field from drain affects channel q More pronounced in small transistors where the drain is closer to the channel q Drain-Induced Barrier Lowering Drain voltage also affect V t Vʹ t = Vt ηvds q High drain voltage causes current to increase. 30

31 Short Channel Effect q In small transistors, source/drain depletion regions extend into the channel Impacts the amount of charge required to invert the channel And thus makes V t a function of channel length q Short channel effect: V t increases with L Some processes exhibit a reverse short channel effect in which V t decreases with L 31

32 Leakage q What about current in cutoff? q Simulated results q What differs? Current doesn t go to 0 in cutoff 32

33 Leakage Sources q Subthreshold conduction Transistors can t abruptly turn ON or OFF Dominant source in contemporary transistors q Gate leakage Tunneling through ultrathin gate dielectric q Junction leakage Reverse-biased PN junction diode current 33

34 Subthreshold Leakage q q q Subthreshold leakage exponential with V gs Vgs Vt 0 + ηvds kγvsb Vds e 1 e nvt vt Ids = Ids0 n is process dependent typically Rewrite relative to I off on log scale q S 100 room temperature 34

35 Gate Leakage q Carriers tunnel thorough very thin gate oxides q Exponentially sensitive to t ox and V DD A and B are tech constants Greater for electrons So nmos gates leak more q Negligible for older processes (t ox > 20 Å) From [Song01] q Critically important at 65 nm and below (t ox 10.5 Å) 35

36 Temperature Sensitivity q Increasing temperature Reduces mobility Reduces V t q I ON decreases with temperature q I OFF increases with temperature I ds increasing temperature V gs 36

37 So What? q So what if transistors are not ideal? They still behave like switches. q But these effects matter for Supply voltage choice Logical effort Quiescent power consumption Pass transistors Temperature of operation 37

38 Parameter Variation q Transistors have uncertainty in parameters Process: L eff, V t, t ox of nmos and pmos Vary around typical (T) values q Fast (F) L eff : short V t : low t ox : thin q Slow (S): opposite q Not all parameters are independent for nmos and pmos slow fast pmos slow SF SS TT nmos FF FS fast 38

39 Environmental Variation q V DD and T also vary in time and space q Fast: V DD : high T: low Corner Voltage Temperature F C T C S C 39

40 Process Corners q Process corners describe worst case variations If a design works in all corners, it will probably work for any variation. q Describe corner with four letters (T, F, S) nmos speed pmos speed Voltage Temperature 40

41 Important Corners q Some critical simulation corners include Purpose nmos pmos V DD Temp Cycle time S S S S Power F F F F Subthreshold leakage F F F S 41

42 Summary q Fundamental transistor theory q Transistors are non-ideal q Leakage can be a big concern while scaling down q Also parameter variation is an issue q Next lecture DC & Transient Response Readings 2.5, : CMOS Transistor Theory CMOS VLSI Design 42

43 Backup Slides CMOS VLSI Design 43

44 Vel Sat I-V Effects q Ideal transistor ON current increases with V DD 2 ( Vgs Vt ) W β I = µ C = V V L ( ) ds ox gs t q Velocity-saturated ON current increases with V DD ( ) I = C W V V v ds ox gs t max q Real transistors are partially velocity saturated Approximate with α-power law model I ds V DD α 2 1 < α < 2 determined empirically ( 1.3 for 65 nm) 44

45 α-power Model 0 Vgs < Vt cutoff Vds Ids = Idsat Vds < Vdsat linear Vdsat Idsat Vds > Vdsat saturation β I = P V V 2 ( ) dsat c gs t α ( ) /2 V = P V V dsat v gs t α 45

46 Channel Length Modulation q Reverse-biased p-n junctions form a depletion region Region between n and p with no carriers Width of depletion L d region grows with reverse bias L eff = L L d q Shorter L eff gives more current GND Source V DD Gate V DD Drain Depletion Region Width: L d I ds increases with V ds Even in saturation n + L L eff p GND n + bulk Si 46

47 Chan Length Mod I-V β I V V V 2 2 ds = gs t 1 +λ ds ( ) ( ) q λ = channel length modulation coefficient not feature size Empirically fit to I-V characteristics 47

48 Junction Leakage q Reverse-biased p-n junctions have some leakage Ordinary diode leakage Band-to-band tunneling (BTBT) Gate-induced drain leakage (GIDL) p+ n+ n+ p+ p+ n+ p substrate n well 48

49 Diode Leakage q Reverse-biased p-n junctions have some leakage VD T I e v D = I S 1 q At any significant negative diode voltage, I D = -I s q I s depends on doping levels And area and perimeter of diffusion regions Typically < 1 fa/µm 2 (negligible) 49

50 Band-to-Band Tunneling q Tunneling across heavily doped p-n junctions Especially sidewall between drain & channel when halo doping is used to increase V t q Increases junction leakage to significant levels X j : sidewall junction depth E g : bandgap voltage A, B: tech constants 50

51 Gate-Induced Drain Leakage q Occurs at overlap between gate and drain Most pronounced when drain is at V DD, gate is at a negative voltage Thwarts efforts to reduce subthreshold leakage using a negative gate voltage 51

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