ECE-305: Fall 2017 MOS Capacitors and Transistors

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1 ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters (pp , ) Professor Peter Bermel Electrical and Computer Engineering Purdue University, West Lafayette, IN USA 11/2/2017 Bermel ECE 305 F17 1

2 MOS capacitor 1) Gate voltage 2) Example problem 3) MOS capacitors 4) MOS field-effect transistors metal / heavily doped polysilicon SiO 2 t ox» 1-2 nm p-si 11/2/2017 Bermel ECE 305 F17 2

3 gate voltage and surface potential DV OX 0 < f S < 2f F = DV OX + f S DV ox = x oe ox DV S E C E i E F E FM Si E V metal =? Gate voltage is surface potential + oxide voltage drop 11/2/ Bermel ECE 305 F17 3

4 band banding in p-type MOS = 0 < 0 0 < < V T > V T f S = 0 f S < 0 0 < f S < 2f F f S > 2f F Flat band Accumulation Depletion Inversion 11/2/2017 Bermel ECE 305 F17 Fig. 16.6, Semiconductor Device Fundamentals, R.F. Pierret 4

5 MOS electrostatics: depletion (results from last time) W = E S = 2k Se 0 f S qn A 2qN Af S k s e 0 Q B = -qn A W f S cm V/cm ( ) C/cm 2 E ( x) E S E S = qn A W k S e 0 1 SW = f S 2 E P Q B = - 2qk s e 0 N A f S C/cm 2 = - Q B ( f S ) + f S W x 0 < f S < 2f F 11/2/2017 Bermel ECE 305 F17 5

6 MOS electrostatics: inversion f ( x) f ( 0) E C f F E i f S» 2f F ff Si E F E V W T é W T = 2K Se 0 ù ê 2f F ë qn ú A û 11/2/2017 Bermel ECE 305 F17 1/2 Maximum depletion region depth 6 x

7 delta-depletion approximation r metal W T = 2k Se 0 2f F qn A -x o W T Q B = -qn A W T x r = -qn A Q 11/2/2017 n Bermel ECE 305 F17 7

8 delta-depletion approximation E ( x) E S E ( 0) = - Q S K S e 0 E ( 0 + ) = - Q B K S e 0 P 11/2/2017 Bermel ECE 305 F17 W x 8

9 MOS electrostatics: inversion f S» 2f F f ( x) f ( 0) = - Q S + 2f F E C = - Q B V T = - Q B ( 2f F ) + Q n ( 2f F ) + 2f F + 2f F f F Si f F E i E F E V Q n = /2/2017 ( ) V T W T é W T = 2K Se 0 ù ê 2f F ë qn ú A û Bermel ECE 305 F17 1/2 9 x

10 MOS capacitor 1) Gate voltage 2) Example problem 3) MOS capacitors 4) MOS field-effect transistors metal / heavily doped polysilicon SiO 2 t ox» 1-2 nm p-si 11/2/2017 Bermel ECE 305 F17 10

11 example Assume n+ poly Si gate channel doping t ox = 1.5 nm S G D What is V T? e-field in oxide at = 1V? source silicon drain SiO 2 11/2/2017 Bermel ECE 305 F17 11

12 example (cont.) = - Q S ( f S ) + f S f F = k BT q ln æ è ç N A n i ö ø f F = 0.48 V V T = - Q B ( 2f F ) V T = f ms - Q B + 2f F ( 2f F ) + 2f F = K O e 0 x o Q B = -qn A W ( 2f F ) Q B = - 2qk s e 0 N A 2f F = F/cm 2 Q B = C/cm 2 V T = 0.14 V f ms = - k T B q ln æ è ç N A N D n i 2 ö ø f ms = V 11/2/2017 Bermel ECE 305 F17 12

13 example (cont) Q n = - ( - V T ) Q n = C/cm 2 Q n q = C/cm 2 E OX = - Q S = - Q + Q n B k ox e 0 k ox e 0 ( 2f B ) E OX = V/cm 11/2/2017 Bermel ECE 305 F17 13

14 MOS capacitor 1) Gate voltage 2) Example problem 3) MOS capacitors 4) MOS field-effect transistors metal / heavily doped polysilicon SiO 2 t ox» 1-2 nm p-si 11/2/2017 Bermel ECE 305 F17 14

15 MOS capacitor + v S sinwt v S sinwt + - ~ + - p-si 11/2/2017 Bermel ECE 305 F17 15

16 MOS capacitor in depletion W ( f S ) W ( ) p-si 11/2/2017 Bermel ECE 305 F17 16

17 MOS capacitor in depletion Gate x o K O W ( f S ) K S C =? Undepleted P-type semiconductor 11/2/2017 Bermel ECE 305 F17 17

18 a simpler problem x o K O = K Oe 0 x o W ( f S ) K S C S = K Se 0 W ( f S ) 18 1 C = C = C C S ox C = C S C S + 11/2/2017 Bermel ECE 305 F17 C = 1 + C S ( ) 1+ K OW f S K S x o

19 result x o k ox W ( f S ) k Si f S C S C = ( ) 1+ K OW f S K S x o 11/2/2017 Bermel ECE 305 F17 19

20 s.s. gate capacitance vs. d.c. gate bias accumulation C depletion C = ( ) 1+ K W f O S K S x o flat band inversion V T 11/2/2017 Bermel ECE 305 F17 20

21 s.s. gate capacitance vs. d.c. gate bias C flat band accumulation depletion C = ( ) 1+ K OW f S K S x o inversion V T 11/2/2017 Bermel ECE 305 F17 21

22 capacitance vs. gate voltage C flat band C = accumulation ( ) 1+ K OW f S K S x o depletion inversion V T 11/2/2017 Bermel ECE 305 F17 22

23 high frequency vs. low frequency C flat band low frequency C = accumulation ( ) 1+ K OW f S K S x o depletion inversion high frequency V T 11/2/2017 Bermel ECE 305 F17 23

24 high frequency vs. low frequency C low frequency high frequency V T 11/2/2017 Bermel ECE 305 F17 24

25 high frequency vs. low frequency n + -Si n + -Si MOS capacitor p-si 11/2/2017 Bermel ECE 305 F17 25

26 MOS capacitor 1) Gate voltage 2) Example problem 3) MOS capacitors 4) MOS field-effect transistors metal / heavily doped polysilicon SiO 2 t ox» 1-2 nm p-si 11/2/2017 Bermel ECE 305 F17 26

27 side and top views of a MOSFET Metal Oxide Semiconductor Field Effect Transistor V S = 0 V D n-si S L D n-si W L p-type silicon SiO 2 source gate drain side view Bermel ECE 305 F17 top view 27

28 transistors 11/2/2017 Bermel ECE 305 F17 28

29 transistor as a black box terminal 1 There are many kinds of transistors: control black box I 1 terminal 2 terminal 4 MOSFET SOI MOSFET SB FET FinFET MODFET (HEMT) bipolar transistor JFET heterojunction bipolar transistor BTBT FET SpinFET 11/2/2017 Bermel ECE 305 F17 29

30 the bulk MOSFET S G D circuit symbol Gate source silicon drain SiO 2 Source I D Drain Body B (Texas Instruments, ~ 2000) 11/2/2017 Bermel ECE 305 F17 30

31 the MOSFET as a 2-port device MOSFET circuit symbol common source Drain Gate I D G D I D output V DS Source S input S current vs. voltage (IV) characteristics I D (,V S,V ) D I D I D ( V ) GS at a fixed V DS ( V ) DS at a fixed S transfer output 31

32 IV characteristics: resistor I + I less resistance I = V R R V more resistance V - I = V R Ohm s Law 11/2/2017 Bermel ECE 305 F17 32

33 IV characteristics: ideal current source I + I I = I 0 I 0 V - V I = I 0 11/2/2017 Bermel ECE 305 F17 33

34 IV characteristics: transistors D I D I D G S1 S n-channel enhancement mode MOSFET gate voltage controlled resistor linear region V DS gate voltage controlled current source saturation region 34

35 IV characteristics: real current sources I + I I 0 I = I 0 + V R 0 R 0 I 0 V V - 11/2/2017 Bermel ECE 305 F17 35

36 IV characteristics: transistors D I D I D G S1 S n-channel enhancement mode MOSFET V DS 11/2/2017 Bermel ECE 305 F17 36

37 MIOSFET IV: output characteristics D I D I D G S S n-channel enhancement mode MOSFET subthreshold region V DS linear region saturation region 11/2/2017 Bermel ECE 305 F17 37

38 output vs. transfer characteristics output characteristics transfer characteristics I D low V DS high V DS D I I D V DS2 > V DS1 G S V DS1 V DSAT V DS V T S saturation voltage threshold voltage Bermel ECE 305 F17 38

39 applications of MOSFETs symbo l switch amplifier D D D G S G S G input signal S output signal 11/2/2017 Bermel ECE 305 F17 39

40 n-channel vs. p-channel MOSFET n-mosfet p-mosfet I D I D V S = 0 > V T V D > 0 V S = 0 < V T V D < 0 n-si S channel D n-si p-si S channel D p-si L L p-type silicon n-type silicon side view side view 11/2/2017 Bermel ECE 305 F17 40

41 MOSFET device metrics I D ( ma mm) on-resistance R ON ( W - mm) output resistance: r d ( W - mm) on-current (ma/μm) I D ( S = V DS = V DD ) S transconductance V DD V DS g m º DI D DS V DS ( ms mm) 11/2/2017 Bermel ECE 305 F17 41

42 MOSFET device metrics (ii) transfer characteristics: I D ( ma mm) I ON V DS = V DD off-current V DS = 0.05 V S V TSAT V TLIN V DD threshold voltage 11/2/

43 MOSFET device metrics (iii) log 10 I D ( ma mm) off-current transfer characteristics: V DS = V DD subthreshold swing: ( mv decade) I ON V DS = 0.05 V DIBL (drain-induced barrier lowering) ( mv V) S V T V DD 11/2/2017 Bermel ECE 305 F17 43

44 summary Given the measured characteristics of a MOSFET, you should be able to determine: 1. on-current: I ON 2. off-current: I OFF 3. subthreshold swing, S 4. drain induced barrier lowering: DIBL 5. threshold voltage: V T (lin) and V T (sat) 6. on resistance: R ON 7. drain saturation voltage: V DSAT 8. output resistance: r o 9. transconductance: g m Our goal is to understand these device metrics. 11/2/2017 Bermel ECE 305 F17 44

45 Example: 32 nm N-MOS technology 11/2/2017 Bermel ECE 305 F17 45

46 conclusions Can calculate the charge distribution, surface potentials, and gate voltage ranges for each MOS regime Can then calculate capacitance as a function of frequency and gate voltage The MOS capacitor is the foundation for MOS field effect transistors, characterized by many device metrics Next time, we will use band structures to estimate the device metrics for MOSFETs 11/2/2017 Bermel ECE 305 F17 46

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