ECE-305: Spring 2016 MOSFET IV

Transcription

1 ECE-305: Spring 2016 MOSFET IV Professor Mark Lundstrom Electrical and Computer Engineering Purdue University, West Lafayette, IN USA Lundstrom s lecture notes: Lecture 4 4/7/16

2 outline 1) Introduction 2) Linear region 3) Saturation region 4) Full range ( = 0 à ) 5) DIBL 6) Series resistance 7) VS model level 0 2

3 Long vs. short channel MOSFETs Square Law Velocity saturated SAT ( V T ) 2 SAT ( V T ) Fig. E17.2, Semiconductor Device 3 Fundamentals, R.F. Pierret

4 the MIT VS Model ß 32 nm technology à 4

5 outline 1) Introduction 2) Linear region 3) Saturation region 4) Full range ( = 0 à ) 5) DIBL 6) Series resistance 7) VS model level 0 5

6 MOSFET IV characteristic circuit symbol gate-voltage controlled current source D G S gate-voltage controlled resistor (Courtesy, Shuji Ikeda, ATDF, Dec. 2007) 6

7 MOSFET e-band (equilibrium) L E = 0 0 > V T = 0 E C ( y) n-si n-si = V DD p-si E F y = 0 y y = 0 y Q n C ox ( V T ) C cm 2 7

8 MOSFET e-band (high, low ) L E 0 > V T n-si n-si E C ( y) = V DD y = 0 p-si y F n E y = 1 q de C dx F n y Q n C ox ( V T ) C cm 2 8

9 MOSFET IV L 0 > V T current is charge per unit time n-si n-si = W Q n ( y) υ y (y) y = 0 p-si y C Q V Q n C ox MOS electrostatics Q n 0 < V T F ( V T ) C cm 2 ( ) C ox = K O ε 0 x o F cm 2 9

10 L MOSFET IV: low 0 > V T Q n ( y) C ox ( V T ) = W Q n Q n = C ox ( y) υ y (y) ( V T ) gate-voltage controlled resistor υ y ( y ) = µ E = W L µ C ( n V V n ox GS T )V y DS E y = L 10

11 outline 1) Introduction 2) Linear region 3) Saturation region 4) Full range ( = 0 à ) 5) DIBL 6) Series resistance 7) VS model level 0 11

12 MOSFET e-band (high, low ) L E virtual source 0 > V T VDS n-si n-si E C ( y) = V DD p-si F n F n y = 0 y y = 0 y Q n C ox ( V T ) C cm 2 12

13 MOSFET IV: pinch-off at high 0 > V T V D Q n ( y) = C ox ( V T V(y) ) V ( y ) pinch = ( V T ) Note: thickness of channel illustrates the areal density of electrons not the actual thickness. Q n ( y ) pinch 0 Electric field is very large in the pinch-off region. 13

14 pinch off in the channel pinch-off point 0 > V T V D E C y ( nm) 14

15 MOSFET IV: high 0 > V T V D V ( y pinch ) = ( V T ) Q n ( y) = C ox ( V T V ( y) ) = W Q n ( y) υ y (y) = W Q n ( 0) υ y (0) Q n ( 0) = C ox ( V T ) υ( 0) = µ n E y ( 0) E y (0) V ( y ) pinch L = ( V T ) L = W L µ C n ox 2 ( V V ) 2 GS T 15

16 short channel MOSFETs SAT ( V T ) 16

17 High : velocity saturation L 1.0V 20nm V/cm velocity cm/s ---> 10 7 υ = µ n E υ = υ sat electric field V/cm ---> 17

18 MOSFET IV: velocity saturation 0 > V T E y >> 10 4 = W Q n ( y) υ y (y) (Courtesy, Shuji Ikeda, ATDF, Dec. 2007) Q n = C ox ( V T ) ( ) υ y = υ sat = W C ox υ sat V T 18

19 outline 1) Introduction 2) Linear region 3) Saturation region 4) Full range ( = 0 à ) 5) DIBL 6) Series resistance 7) VS model level 0 19

20 MOSFET: IV (re-cap) LIN = W L µ nc ox ( V T ) SAT = W C ox υ sat AT = υ satl µ n ( V T ) AT We have developed a 2-piece approximation to the MOSFET IV characteristic. 20

21 piecewise model for (, ) W = Q n ( ) υ( ) V T : Q n ( ) = C ox ( V T ) < V T : Q n ( ) = 0 AT : υ ( ) = µ n > AT : υ( ) = υ sat L If we can make the average velocity go smoothly from the low to high limits, then we will have a smooth model for (, ) above threshold. 21

22 From low to high 1 υ( ) = 1 µ n L + 1 υ sat υ( ) = AT 1+ AT υ sat υ( ) = F SAT ( )υ sat F SAT ( ) = AT ( ) β 1+ V DSAT 1/β The extra parameter, β, is empirically adjusted to fit the IV characteristic. Typically, β for both N- MOSFETs and for P-MOSFETs. 22

23 empirical saturation function υ( ) = F SAT ( )υ sat F SAT ( ) AT ( ) β 1+ V DSAT 1/β << AT : F SAT ( ) V >> AT : F SAT ( ) 1 DSAT υ( ) υ sat AT υ( ) υ sat υ sat L µ n υ( ) υ sat V υ( ) µ DS n L 23

24 saturation function: F SAT (V D ) υ( ) = F SAT ( )υ sat F SAT ( ) = AT ( ) β 1+ V DSAT 1/β Although this is just an empirical method to produce smooth curve that properly goes between the small and large V D limits, it works very well in practice, which suggests that it captures something important about MOSFETs. 24

25 outline 1) Introduction 2) Linear region 3) Saturation region 4) Full range ( = 0 à ) 5) DIBL 6) Series resistance 7) VS model level 0 25

26 output resistance need to treat the finite output resistance = W Q n υ sat Q n = C ox ( V T ) V T = V T 0 δ AT δ = DIBL mv V 26

27 outline 1) Introduction 2) Linear region 3) Saturation region 4) Full range ( = 0 à ) 5) DIBL 6) Series resistance 7) VS model level 0 27

28 intrinsic vs. extrinsic voltages V D R D D V G = V G V G = V G V D = V D ( V G, V S, V D )R D G V S = V S + ( V G, V S, V D )R S silicon S R S V S 28

29 effect of series resistances = W C ox υ sat ( V T ) = R ch = R S = ( R ch + R S + R ) D 29

30 outline 1) Introduction 2) Linear region 3) Saturation region 4) Full range ( = 0 à ) 5) DIBL 6) Series resistance 7) Simple VS model 30

31 Simple VS model 1) W = Q n ( ) υ ( ) 2) ( ) = C ox ( ) Q n V T = V T 0 δ V T ( > V T ) There are only 8 devicespecific parameters in this model: 3) ( ) = F SAT υ ( )υ sat C ox,v T,δ,υ sat,µ n, L 4) F SAT ( ) = 1+ AT ( ) β AT 1/β R SD = R S + R D + β 5) AT = υ sat L µ n 31

32 outline 1) Introduction 2) Linear region 3) Saturation region 4) Full range ( = 0 à ) 5) DIBL 6) Series resistance 7) Simple VS model 8) Summary 32

33 MOSFET IV: low = W C ox υ sat ( V T ) gate-voltage controlled resistor = W L µ n C ox ( V T ) 33

34 sub-micron MOSFETs square law theory (pinch-off) = W L µ C n ox 2 ( V V ) 2 GS T velocity saturation theory = W C ox υ sat ( V T ) 34

35 the MIT VS Model ß 32 nm technology à 35

36 the MIT VS Model 1 1 µ n µ app υ sat υ inj apparent mobility injection velocity 36