# Lecture 11: J-FET and MOSFET

Size: px
Start display at page:

Transcription

1 ENE 311 Lecture 11: J-FET and MOSFET

2 FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices. FETs have a higher input impedance. BJTs have higher gains. FETs are less sensitive to temperature variations and are more easily integrated on ICs. 2

3 Current Controlled vs oltage Controlled Devices January 2004 ELEC 121 3

4 Transfer Characteristics The input-output transfer characteristic of the JFET is not as straight forward as it is for the BJT In a BJT, β (hfe) defined the relationship between I B (input current) and I C (output current). In a JFET, the relationship (Shockley s Equation) between GS (input voltage) and I D (output current) is used to define the transfer characteristics, and a little more complicated (and not linear): I D = I DSS 1 - As a result, FET s are often referred to a square law devices GS P 2 January 2004 ELEC 121 4

5 FET Types JFET: Junction FET MOSFET: Metal Oxide Semiconductor FET D-MOSFET: Depletion MOSFET E-MOSFET: Enhancement MOSFET 5

6 There are two types of JFETs n-channel p-channel The n-channel is more widely used. JFET Construction There are three terminals: Drain (D) and Source (S) are connected to the n-channel Gate (G) is connected to the p-type material 6

7 JFET Operation: The Basic Idea JFET operation can be compared to a water spigot. The source of water pressure is the accumulation of electrons at the negative pole of the drain-source voltage. The drain of water is the electron deficiency (or holes) at the positive pole of the applied voltage. The control of flow of water is the gate voltage that controls the width of the n-channel and, therefore, the flow of charges from source to drain. 7

8 N-Channel JFET Symbol 8

9 JFET Operating Characteristics There are three basic operating conditions for a JFET: GS = 0, DS increasing to some positive value GS < 0, DS at some positive value oltage-controlled resistor 9

10 JFET Operating Characteristics: GS = 0 Three things happen when GS = 0 and DS is increased from 0 to a more positive voltage The depletion region between p-gate and n-channel increases as electrons from n-channel combine with holes from p-gate. Increasing the depletion region, decreases the size of the n-channel which increases the resistance of the n-channel. Even though the n-channel resistance is increasing, the current (I D ) from source to drain through the n- channel is increasing. This is because DS is increasing. 10

11 JFET Operating Characteristics: Pinch Off If GS = 0 and DS is further increased to a more positive voltage, then the depletion zone gets so large that it pinches off the n-channel. This suggests that the current in the n- channel (I D ) would drop to 0A, but it does just the opposite as DS increases, so does I D. 11

12 JFET Operating Characteristics: : Saturation At the pinch-off point: Any further increase in GS does not produce any increase in I D. GS at pinch-off is denoted as p. I D is at saturation or maximum. It is referred to as I DSS. The ohmic value of the channel is maximum. 12

13 JFET Operating Characteristics As GS becomes more negative, the depletion region increases. 13

14 JFET Operating Characteristics As GS becomes more negative: The JFET experiences pinch-off at a lower voltage ( P ). I D decreases (I D < I DSS ) even though DS is increased. Eventually I D reaches 0 A. GS at this point is called p or GS(off).. Also note that at high levels of DS the JFET reaches a breakdown situation. I D increases uncontrollably if DS > DSmax. 14

15 The region to the left of the pinch-off point is called the ohmic region. The JFET can be used as a variable resistor, where GS controls the drain-source resistance (r d ). As GS becomes more negative, the resistance (r d ) increases. JFET Operating Characteristics: oltage-controlled Resistor r d = 1 r o GS P 2 15

16 Transfer (Transconductance) Curve From this graph it is easy to determine the value of I D for a given value of GS It is also possible to determine IDSS and P by looking at the knee where GS is 0

17 Plotting the JFET Transfer Curve Using I DSS and p ( GS(off) ) values found in a specification sheet, the transfer curve can be plotted according to these three steps: Solving for GS = 0 Step 1 I D = I DSS I D = I DSS 1 GS P 2 Step 2 Solving for GS = p ( GS(off) ) I D = 0A I D = I DSS 1 GS P 2 Solving for GS Step 3 = 0 to p I D = I DSS 1 GS P 2 17

18 JFET Transfer Characteristics The transfer characteristic of input-to-output is not as straightforward in a JFET as it is in a BJT. In a BJT, β indicates the relationship between I B (input) and I C (output). I = f ( I ) =β I C B B In a JFET, the relationship of GS (input) and I D (output) is a little more complicated: I D = I DSS 1 where GS is the control variable, P and I DSS are constants. GS P 2 NOTE: When GS = 0, I D = I DSS When GS = P, I D = 0 ma 18

19 p-channel JFETS The p-channel JFET behaves the same as the n-channel JFET, except the voltage polarities and current directions are reversed. 19

20 p-channel JFET Characteristics As GS increases more positively The depletion zone increases I D decreases (I D < I DSS ) Eventually I D = 0 A Also note that at high levels of DS the JFET reaches a breakdown situation: I D increases uncontrollably if DS > DSmax. 20

### Chapter 6: Field-Effect Transistors

Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled

### JFET Operating Characteristics: V GS = 0 V 14. JFET Operating Characteristics: V GS = 0 V 15

J Operating Characteristics: V GS = 0 V 14 V GS = 0 and V DS increases from 0 to a more positive voltage: Gate and Source terminals: at the same potential Drain: at positive potential => reverse biased

### ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

### CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012

1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET D-FET (Depletion MOS) MOSFET (Enhancement E-FET) DC biasing Small signal

### Chapter7. FET Biasing

Chapter7. J configurations Fixed biasing Self biasing & Common Gate Voltage divider MOS configurations Depletion-type Enhancement-type JFET: Fixed Biasing Example 7.1: As shown in the figure, it is the

### Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

### Electronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi

Electronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi Module No. #05 Lecture No. #02 FETS and MOSFETS (contd.) In the previous lecture, we studied the working

### Capacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009

Wilfrid Laurier University June 4, 2009 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists of two conductive

### MOSFET Physics: The Long Channel Approximation

MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The

### Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

### Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

### KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 7 DC BIASING FETS (CONT D)

KOM751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU Control and Automation Dept. 1 7 DC BIASING FETS (CONT D) Most of the content is from the textbook: Electronic devices and circuit theory, Robert

### Field-Effect (FET) transistors

Field-Effect (FET) transistors References: Barbow (Chapter 8), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and, therefore, its current-carrying

### Metal-Oxide-Semiconductor Field Effect Transistor

Symbols Structure Operating principle Terminal characteristics Operating regions Quiescent point position Metal-Oxide-Semiconductor Field Effect Transistor n-channel and p-channel enhancement-type MOSFET

### Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

### Figure 1: MOSFET symbols.

c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between

### à FIELD EFFECT TRANSISTORS

Prof.M.G.Guvench à FIELD EFFECT TRANSISTORS ü FET: CONTENTS Principles of Operation Models: DC, S.S.A.C. and SPICE Applications: AC coupled S.S. Amplifiers ü FET: NAMES JFET Junction Field Effect Transistor

### 5. EXPERIMENT 5. JFET NOISE MEASURE- MENTS

5. EXPERIMENT 5. JFET NOISE MEASURE- MENTS 5.1 Object The objects of this experiment are to measure the spectral density of the noise current output of a JFET, to compare the measured spectral density

### CLASS 12&13 JFET PARAMETERS AND BIASING

CLASS 12&13 JFET PARAMETERS AN BIASING The family of drain characteristic curves shows that when GS becomes more negative, Sp (or S(sat) )andi S become smaller. I is dependent on the width of the channel.

### ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

### Vidyalankar S.E. Sem. III [EXTC] Analog Electronics - I Prelim Question Paper Solution

. (a) S.E. Sem. [EXTC] Analog Electronics - Prelim Question Paper Solution Comparison between BJT and JFET BJT JFET ) BJT is a bipolar device, both majority JFET is an unipolar device, electron and minority

### Monolithic N-Channel JFET Duals

Monolithic N-Channel JFET Duals N96/97/98/99 Part Number V GS(off) (V) V (BR)GSS Min (V) Min (ms) I G Max (pa) V GS V GS Max (mv) N96.7 to N97.7 to N98.7 to N99.7 to Monolithic Design High Slew Rate Low

### 2N5545/46/47/JANTX/JANTXV

N//7/JANTX/JANTXV Monolithic N-Channel JFET Duals Product Summary Part Number V GS(off) (V) V (BR)GSS Min (V) g fs Min (ms) I G Max (pa) V GS V GS Max (mv) N. to.. N. to.. N7. to.. Features Benefits Applications

### Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

### ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

### EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

### Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor

JFETs AND MESFETs Introduction Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor Why would an FET made of a planar capacitor with two metal plates, as

### The Gradual Channel Approximation for the MOSFET:

6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

### Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

### Current mechanisms Exam January 27, 2012

Current mechanisms Exam January 27, 2012 There are four mechanisms that typically cause currents to flow: thermionic emission, diffusion, drift, and tunneling. Explain briefly which kind of current mechanisms

### Monolithic N-Channel JFET Dual

N9 Monolithic N-Channel JFET Dual V GS(off) (V) V (BR)GSS Min (V) g fs Min (ms) I G Max (pa) V GS V GS Max (mv). to. Monolithic Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: pa Low Noise:

### EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

### DATA SHEET. BF246A; BF246B; BF246C; BF247A; BF247B; BF247C N-channel silicon junction field-effect transistors DISCRETE SEMICONDUCTORS

DISCRETE SEMICONDUCTORS DATA SHEET Supersedes data of April 1995 File under Discrete Semiconductors, SC07 1996 Jul 29 FEATURES Interchangeability of drain and source connections High I DSS range Frequency

### MOS Transistor Properties Review

MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

### Homework Assignment 09

Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

### Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

### J/SST111 Series. N-Channel JFETs. Vishay Siliconix J111 SST111 J112 SST112 J113 SST113

N-Channel JFETs J SST J SST J SST Part Number V GS(off) (V) r DS(on) Max ( ) I D(off) Typ (pa) t ON Typ (ns) J/SST to 5 4 J/SST to 5 5 5 4 J/SST 5 4 Low On-Resistance: < Fast Switching t ON : 4 ns Low

### Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

### 6.012 Electronic Devices and Circuits

Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

### EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

### EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

### SOME USEFUL NETWORK THEOREMS

APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem

### ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

### Biasing the CE Amplifier

Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

### ECE 145A/218A Power Amplifier Design Lectures. Power Amplifier Design 1

Power Amplifiers; Part 1 Class A Device Limitations Large signal output match Define efficiency, power-added efficiency Class A operating conditions Thermal resistance We have studied the design of small-signal

### (Refer Slide Time: 1:49)

Analog Electronic Circuits Professor S. C. Dutta Roy Department of Electrical Engineering Indian Institute of Technology Delhi Lecture no 14 Module no 01 Midband analysis of FET Amplifiers (Refer Slide

### The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

### MOS Capacitors ECE 2204

MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field

### Monolithic N-Channel JFET Dual

SST Monolithic N-Channel JFET Dual V GS(off) (V) V (BR)GSS Min (V) Min (ms) I G Typ (pa) V GS V GS Max (mv) to 6. Monolithic Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: pa Low Noise

### Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

### Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

### ECE315 / ECE515 Lecture-2 Date:

Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode

### R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition Figures for Chapter 6 Free electron Conduction band Hole W g W C Forbidden Band or Bandgap W V Electron energy Hole Valence

### Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

Metal-Oxide-Semiconductor ield Effect Transistor (MOSET) Source Gate Drain p p n- substrate - SUB MOSET is a symmetrical device in the most general case (for example, in an integrating circuit) In a separate

### Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)

Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture

### Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2

### ! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)

ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating

### MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

### Lecture 4: CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

### GaN based transistors

GaN based transistors S FP FP dielectric G SiO 2 Al x Ga 1-x N barrier i-gan Buffer i-sic D Transistors "The Transistor was probably the most important invention of the 20th Century The American Institute

### Digital Electronics Part II - Circuits

Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The

### MOS Transistor Theory

MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

### SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

### EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues

EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley

### EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2

### ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

### Matched N-Channel JFET Pairs

Matched N-Channel JFET Pairs N// PRODUCT SUMMARY Part Number V GS(off) (V) V (BR)GSS Min (V) g fs Min I G Typ (pa) V GS V GS Max (mv) N. to 7. N. to 7. N. to 7. FEATURES BENEFITS APPLICATIONS Two-Chip

### II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

14ECEI302/EC 212 1. Answer all questions (1X12=12 Marks) a What are the applications of linked list? b Compare singly linked list and doubly linked list. c Define ADT. d What are the basic operations of

### JFET Homework. Nov. 4, 2007, rev. Nov. 12, 2015

Nov. 4, 2007, rev. Nov. 12, 2015 These homework problems provide practice with analysis and design involving the most common type of JFET circuits. There is one problem for each type of circuit. Answers

### 2N4856JAN/JANTX/JANTXV Series. N-Channel JFETs. Vishay Siliconix

N-Channel JFETs 2N4856JAN 2N4856JANTX 2N4856JANTX 2N4857JAN 2N4857JANTX 2N4857JANTX 2N4858JAN 2N4858JANTX 2N4858JANTX 2N4859JAN 2N4859JANTX 2N4859JANTX 2N4860JAN 2N4860JANTX 2N4860JANTX 2N4861JAN 2N4861JANTX

### Chapter 3. FET Amplifiers. Spring th Semester Mechatronics SZABIST, Karachi. Course Support

Chapter 3 Spring 2012 4 th Semester Mechatronics SZABIST, Karachi 2 Course Support humera.rafique@szabist.edu.pk Office: 100 Campus (404) Official: ZABdesk https://sites.google.com/site/zabistmechatronics/home/spring-2012/ecd

### 6.012 Electronic Devices and Circuits

Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

### Typical example of the FET: MEtal Semiconductor FET (MESFET)

Typical example of the FET: MEtal Semiconductor FET (MESFET) Conducting channel (RED) is made of highly doped material. The electron concentration in the channel n = the donor impurity concentration N

### in Electronic Devices and Circuits

in Electronic Devices and Circuits Noise is any unwanted excitation of a circuit, any input that is not an information-bearing signal. Noise comes from External sources: Unintended coupling with other

### Matched N-Channel JFET Pairs

Matched N-Channel JFET Pairs N// PRODUCT SUMMARY Part Number V GS(off) (V) V (BR)GSS Min (V) g fs Min I G Typ (pa) V GS V GS Max (mv) N. to 7. N. to 7. N. to 7. FEATURES BENEFITS APPLICATIONS Two-Chip

### MOS Transistor I-V Characteristics and Parasitics

ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

### Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

### MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste

### Homework Assignment 08

Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

### 2SJ182(L), 2SJ182(S)

Silicon P-Channel MOS FET November 1996 Application High speed power switching Features Low on-resistance High speed switching Low drive current 4 V gate drive device Can be driven from V source Suitable

### Monolithic N-Channel JFET Dual

N98 Monolithic N-Channel JFET Dual V GS(off) (V) V (BR)GSS Min (V) g fs Min (ms) I G Max (pa) V GS V GS Max (mv). to. Monolithic Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: pa Low

### EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

### Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 -

6.012 - Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - Posted on Stellar. Due net Wednesday. Qualitative description - MOS in thermal equilibrium

### Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

### Lecture 04 Review of MOSFET

ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

### Introduction to Power Semiconductor Devices

ECE442 Power Semiconductor Devices and Integrated Circuits Introduction to Power Semiconductor Devices Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Semiconductor Devices Applications System Ratings

### Introduction and Background

Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments

### Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

### Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to

### Session 0: Review of Solid State Devices. From Atom to Transistor

Session 0: Review of Solid State Devices From Atom to Transistor 1 Objective To Understand: how Diodes, and Transistors operate! p n p+ n p- n+ n+ p 2 21 Century Alchemy! Ohm s law resistivity Resistivity

### Lecture 3: Transistor as an thermonic switch

Lecture 3: Transistor as an thermonic switch 2016-01-21 Lecture 3, High Speed Devices 2016 1 Lecture 3: Transistors as an thermionic switch Reading Guide: 54-57 in Jena Transistor metrics Reservoir equilibrium

### Charge-Storage Elements: Base-Charging Capacitance C b

Charge-Storage Elements: Base-Charging Capacitance C b * Minority electrons are stored in the base -- this charge q NB is a function of the base-emitter voltage * base is still neutral... majority carriers

### CPC3730CTR. 350V N-Channel Depletion-Mode FET (SOT-89) INTEGRATED CIRCUITS DIVISION

V (BR)DSX / V (BR)DGX R DS(on) (max) I DSS (min) Package 35V P 3 14mA SOT-89 Features Low R DS(on) at Cold Temperatures R DS(on) 3 max. at 25ºC High Input Impedance High Breakdown Voltage: 35V P Low (off)

### Practice 3: Semiconductors

Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

### 2SJ332(L), 2SJ332(S)

Silicon P-Channel MOS FET November 1996 Application High speed power switching Features Low on-resistance High speed switching Low drive current 4 V gate drive device can be driven from V source Suitable

### P-Channel Enhancement Mode Mosfet

WPM34 WPM34 P-Channel Enhancement Mode Mosfet Http://www.sh-willsemi.com Features Higher Efficiency Extending Battery Life Miniature SOT3-3 Surface Mount Package Super high density cell design for extremely

### Metal-oxide-semiconductor field effect transistors (2 lectures)

Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -