GaN based transistors

Transcription

1 GaN based transistors S FP FP dielectric G SiO 2 Al x Ga 1-x N barrier i-gan Buffer i-sic D

2 Transistors "The Transistor was probably the most important invention of the 20th Century The American Institute of Physics Nobel Prizes: 1956 The prize was awarded jointly, one third each, to: WILLIAM SHOCKLEY, JOHN BARDEEN and WALTER HOUSER BRATTAIN for their researches on semiconductors and their discovery of the transistor effect The prize is being awarded with one half jointly to: ZHORES I. ALFEROV, and HERBERT KROEMER for developing semiconductor heterostructures used in high-speed- and opto-electronics and one half to: JACK ST. CLAIR KILBY for his part in the invention of the integrated circuit

3 Transistors First Transistor, 1947 First Integrated Circuit, 1958 Intel s 1.7 Billion Transistor Chip 2004

4 Field-Effect Transistor (FET) principles + - Metal Semiconductor - + Metal Semiconductor Lots of electrons No electrons G + G + - S D S D Semiconductor Semiconductor Lots of electrons high S-D current No electrons no S-D current

5 FET principles Any FET device is very similar to a plain capacitor V A Metal d Semiconductor Let the area of the capacitor plates be A. The induced charge Q can be expressed as Q = q A n S, where q = C is the electron charge, n S is the SURFACE CONCENTRATION of induced electrons, n S = Q / (q A); What is the surface concentration? The bulk charge density, n the layer thickness, a; then the surface concentration, n S = n a 1x1 cm 2 a

6 Estimation of induced charge V A Metal d Semiconductor For the PLAIN CAPACITOR, C = ε ε 0 A/d Q = C V = ε ε 0 A V/d, The charge per unit area, Q 1 = ε ε 0 V/d The induced concentration of electrons in the top (metal) plate: n SM = - ε ε 0 V/(q d) <0 (depletion) in the bottom (semiconductor) plate: n S = ε ε 0 V/(q d) >0 (accumulation)

7 Estimation of the induced charge ε = ε r ε 0 ; For the gap filled with dielectric, ε r = 10; ε 0 = F/m; Let d = 0.1 µm; V = 10 V; n S = ε r ε 0 V/(q d) n s m -2 = cm -2 ; In semiconductor films, the n S cm -2; In 1 µm thick metal film, n SM cm -2 >> n S ; No conductivity modulation in the metal plate Significant conductivity modulation in the semiconductor film In this example, the semiconductor film with the equilibrium surface electron concentration of cm -2 would be completely depleted by applying 10 V at the gate

8 The threshold voltage of FETs Suppose the semiconductor plate is doped with donor concentration N D; The equilibrium electron concentration in the semiconductor, n 0 = N D ; For the layer thickness, a, the surface concentration n S0 = N D a; The voltage needed to deplete the entire active layer ( the semiconductor plate) is referred to as the THRESHOLD VOLTAGE of the FET For the n-doped layer the threshold voltage is negative in order to repulse the electrons. The induced concentration at the threshold has to compensate the equilibrium one: n ST = ε ε 0 V T /(q d) = - n S0 Therefore, V T = - q d n S0 / (ε ε 0 )

9 The charge control model of FETs At the threshold the net concentration in the channel is zero: n ST n S0 = 0, where n ST = ε ε 0 V T /(q d) When the applied gate voltage is above the threshold, V G > V T, n S = ε ε 0 V G /(q d) n S = n S n ST = ε ε 0 /(q d) (V G V T ) Note, ε ε 0 /d = C 1 the gap capacitance per unit area Therefore, n S = (C 1 /q) (V G V T ) The above model is referred to as charge control model of FETs

10 FET channel current The current through the channel is I V R = D where V D is the voltage applied between the DRAIN and the SOURCE The gate length L G V 0 + V- - + G S Semiconductor D We are assuming that V D << V T The channel resistance, R (Z is the device width, a is the channel thickness): The channel current : L L R = G = G q n µ a Z q n µ Z I = q n s s ( V L G G ) µ Z V D

11 FET transconductance In the amplifier circuit, the input signal is applied at the gate, the drain current modulates the output voltage. The transconductance, g m = di/dv G measures the amplifier gain. I q n ( V ) µ Z q n µ Z = s G VD g s m = 0 VD LG VT LG The main factors affecting FET performance (for any FET type): n s, µ I and g m L G I and g m Highest carrier concentration and mobility in the channel and shortest gate length are key performance parameters of any FET

12 FET speed of response The gate length L G V D + V- - + G S Semiconductor The time it takes the electrons to drift under the gate: L t dr = v v S is the electron saturation velocity (limited by scattering) The corresponding FET cutoff frequency, f T dr G S 1 v = = S 2π t 2π L High speed operation requires short gate length and high electron velocity. G D

13 Effects of high drain bias on FET characteristics MOSFET JFET + V G Source Gate Drain + VD The gate- to drain voltage difference depends on the position along the gate So does the induced charge

14 Effects of high drain bias on FET characteristics The particular range of the gate voltage depends on the device type The channel narrowing at the drain edge of the gate causes current saturation in the FETs

15 Effects of high drain bias on FET characteristics Electron velocity saturation due to high electric field in the channel Velocity saturation due to high electric field in the channel also results in the I-V saturation The average electric field in the channel, E av ~ V D /L Can be extremely high for small L I = V 0 µ Z C 1 (V G V T )/L I = v S Z C 1 (V G V T ) v = µ E ~ µ V D /L

16 Different types of FETs Metal - Oxide - Semiconductor FET (MOSFET) d W The gate-channel insulator is made out of dielectric (SiO 2 ), ε = 3.9

17 Different types of FETs Junction FET (JFET) a 0 W a The gate-channel insulator consists of the DEPLETION REGION, i.e. the same material as the channel. For GaAs, ε ~ 12; for GaN ε ~ 9.

18 Different types of FETs Metal-Semiconductor FET (MESFET) a 0 a The gate is formed by Schottky barrier to the semiconductor layer. The gate-channel insulator consists of the DEPLETION REGION, i.e. the same material as the channel. Very similar to the JFET

19 Performance limitations in FETs Doping dependence of carrier mobility (Si) Mobility/velocity degradation at high n S results in poor g m and f T g m = q n V s0 T µ Z V L G D f T 1 v = = S 2π t 2π L dr G

20 The mechanism of mobility degradation in highly doped layers 1) Mobility depends on the interactions between electrons and phonons and impurities. For the phonon scattering, the dependence of mobility on temperature: For the impurity scattering, the dependence of mobility on impurity concentration, N: When the dependence on both temperature and impurities is taken into account,

21 The mechanism of mobility degradation in highly doped layers Concentration dependence of electron mobility T = 300 K

22 The mechanism of velocity degradation in highly doped layers Electron Drift velocity The electron accelerates in the electric field until it gains enough energy to excite lattice vibrations: m n v 2 n max = E n E o hω l 2 where vnmax is the maximum electron drift velocity. Then the scattering process occurs, and the electron loses all the excess energy and all the drift velocity. Hence, the electron drift velocity varies between zero and vn max, and average electron drift velocity (v n = v nmax /2) becomes nearly independent of the electric field: v n hω l 2m n = v sn Typically, v sn 10 5 m/s. Indeed, the measured drift velocity becomes nearly constant in high electric fields

23 The mechanism of mobility degradation in highly doped layers Electron Drift velocity 3 InGaAs InP electron velocity (100,000 m/s) GaAs Heavily doped Si T = 300 K electric field (kv/cm) In the heavily doped materials the peak electron velocity is lower

24 Performance limitations in FETs Any type of FET using channel doping to provide high channel currents suffers from transconductance/speed of response degradation Channel Doping increases n S and channel current increase Electron mobility and velocity decrease g m and f T increase slowly or decrease JFET, MOSFET, MESFET