FieldEffect (FET) transistors


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1 FieldEffect (FET) transistors References: Barbow (Chapter 8), Rizzoni (chapters 8 & 9) In a fieldeffect transistor (FET), the width of a conducting channel in a semiconductor and, therefore, its currentcarrying capability, is varied by the application of an electric field (thus, the name fieldeffect transistor). As such, a FET is a voltagecontrolled device. The most widely used FETs are MetalOxideemiconductor FETs (or MOFET). MOFET can be manufactured as enhancementtype or depletiontype MOFETs. Another type of FET is the Junction FieldEffect Transistors (JFET) which is not based on metaloxide fabrication technique. FETs in each of these three categories can be fabricated either as a nchannel device or a pchannel device. As transistors in these 6 FET categories behave in a very similar fashion, we will focus below on the operation of enhancement MOFETs that are the most popular. nchannel EnhancementType MOFET (NMO) The physical structure of a nchannel EnhancementType MOFET (NMO) is shown. The device is fabricated on a ptype substrate (or Body). Two heavily doped ntype regions (ource and rain) are created in the substrate. A thin (fraction of micron) layer of io 2, which is an excellent electrical insulator, is deposited between source and drain region. Metal is deposited on the insulator to form the ate of the device (thus, metaloxide semiconductor). Metal contacts are also made to the source, drain, and body region. To see the operation of a NMO, let s ground the source and the body and apply a voltage v between the gate and the source, as is shown above. This voltage repels the holes in the ptype substrate near the gate region, lowering the concentration of the holes. As v increases, hole concentration decreases, and the region near gate behaves progressively more like intrinsic semiconductor material (when excess hole concentration is zero) and then, finally, like a ntype material as electrons from n + electrodes (source and drain) enter this region. As a result, when v become larger than a threshold voltage, V t, a narrow layer ECE60L Lecture Notes, pring
2 between source and drain regions is created that is populated with ntype charges (see figure). The thickness of this channel is controlled by the applied v (it is proportional to v V t ). As can be seen, this device works as a channel is induced in the semiconductor and this channel contains ntype charges (thus, nchannel MOFET). In addition, increasing v increases channel width (enhances it). Therefore, this is an nchannel Enhancementtype MOFET or Enhancementtype NMO. Now for a given values of v > V t (so that the channel is formed), let s apply a small and positive voltage v between drain and source. Then, electrons from n + source region enter the channel and reach the drain. If v is increased, current i flowing through the channel increases. Effectively, the device acts like a resistor; its resistance is set by the dimension of the channel and its ntype charge concentration. In this regime, plot of i versus v is a straight line (for a given values of v > V t ) as is shown. The slope of i versus v line is the conductance of the channel. For v V t no channel exists (zero conductance). As value of v V t increases, channel becomes wider and its conductivity increases (because its ntype charge concentration increases). Therefore, the channel conductance (slope of i versus v line) increases with any increase in v V t as is shown above. The above description is correct for small values of v as in that case, v = v v v and the induced channel is fairly uniform (i.e., has the same width near the drain as it has near the source). For a given v > V t, if we now increase v, v = v v becomes smaller than v. As such the size of channel near drain becomes smaller compared to its size near the source, as is shown. As the size of channel become smaller, its resistance increases and the curve of i versus v starts to roll over, as is shown below. ECE60L Lecture Notes, pring
3 For values of v = V t (or v = v V t ), width of the channel approaches zero near the drain (channel is pinched off). Increasing v beyond this value has little effect (no effect in our simple picture) on the channel shape, and the current through the channel remains constant at the value reached when v = v V t. o when the channel is pinched off, i only depends on v (right figure below). NMO Characteristic Curves i versus v in the active (or saturation) regime In sum, a FET can operate in three regimes: 1) Cutoff regime in which no channel exists (v < V t for NMO) and i = 0 for any v. 2) Ohmic or Triode regime in which the channel is formed and not pinched off (v > V t and v v V t for NMO) and FET behaves as a voltagecontrolled resistor. 3) Active or aturation regime in which the channel is pinched off (v V t and v > v V t for NMO) and i does not change with v. everal important point should be noted: 1) No current flows into the gate, i = 0 (note the insulator between gate and the body). 2) FET acts as a voltagecontrolled resistor in the ohmic region. In addition, when v v, FET would act as a linear resistor. 3) When FET is in cutoff, i = 0. However, if i = 0, this does not mean that FET is in cutoff. FET is in cutoff only when a channel does not exist (v < V t ) and i = 0 for any applied v. On the other hand, FET can be in ohmic region, i.e., a channel is formed, but i = 0 because v = 0. ECE60L Lecture Notes, pring
4 4) The third regime is called saturation in most electronic books because i is saturated in this regime and does not increase further. This is a rather unfortunate name as saturation regime in a FET means very different thing than it does in a BJT. ome newer books call this regime active (as it equivalent to activelinear regime of a BJT). 5) The transition between ohmic and active region is clearly defined by v = v V t the point where the channel is pinched off. The i versus v characteristic curves of a FET look very similar to i C versus v CE characteristics curves of a BJT. In fact, as there is a unique relationship between i B and v BE, the i C versus v CE characteristic curves of a BJT can be labeled with different values of v BE instead of i B, making the characteristic curves of the two devices even more similar. In FET v control device behavior and in BJT v BE. Both devices are in cutoff when the input voltage is below a threshold value: v BE < v γ for BJT and v < V t for NMO. They exhibit an active regime in which the output current (i C or i ) is roughly constant as the output voltage (v CE or v ) is changed. There are, however, major differences. Most importantly, a BJT requires i B to operate but in a FET i = 0 (actually very small). These differences become clearer as we explore FETs. As can be seen from NMO physical structure, the device is symmetric, that is position of drain and source can be replaced without any change in device properties. The circuit symbol for a NMO is shown on the right. For most applications, however, the body is connected to the source, leading to a 3terminal element. In that case, source and drain are not interchangeable. A simplified circuit symbol for this configuration is usually used. By convention, current i flows into the drain for a NMO (see figure). As i = 0, the same current will flow out of the source. irection of arrows used to identify semiconductor types in a transistor may appear confusing. The arrows do NOT represent the direction of current flow in the device. Rather, they denote the direction of the underlying pn junction. For a NMO, the arrow is placed on the body and pointing inward as the body is made of ptype material. (Arrow is not on source or drain as they are interchangeable.) In the simplified symbol for the case when body and source is connected, arrow is on the source (device is not symmetric now) and is pointing outward as the source is made of ntype materials. (i.,e. arrow pointing inward for ptype, arrow pointing outward for ntype). i B i ECE60L Lecture Notes, pring
5 NMO i versus v Characteristics Equations Like BJT, a NMO (with source connected to body) has six parameters (three voltages and three currents), two of which (i and v ) can be found in terms of the other four by KVL and KCL. NMO is simpler than BJT because i = 0 (and i = i ). Therefore, three parameters describe behavior of a NMO (v, i, and v ). NMO has one characteristics equation that relates these three parameters. Again, situation is simpler than BJT as simple but accurate characteristics equations exist. Cutoff: v < V t, i = 0 for any v Ohmic: v > V t, i = K[2v (v V t ) v 2 ] for v < v V t Active: v > V t, i = K(v V t ) 2 for v > v V t In the above, K and V t are constants that depend on manufacturing of the NMO (given in manufacturer spec sheets). As mentioned above, for small values of v (v v V t ), NMO behaves as resistor, r, and the value of r is controlled by v V t. This can be seen by dropping v 2 in i equation of ohmic regime: r = v i 1 2K(v V t ) How to olve NMO Circuits: olution method is very similar to BJT circuit (actually simpler because i = 0). To solve, we assume that NMO is in a particular state, use NMO model for that state to solve the circuit and check the validity of our assumption by checking the inequalities in the model for that state. A formal procedure is: 1) Write down a KVL including terminals (call it KVL). 2) Write down a KVL including terminals (call it KVL). 3) From KVL, compute v (using i = 0) 3a) If v < V t, NMO is in cutoff. Let i = 0, solve for v from KVL. We are done. 3b) If v > V t, NMO is not in cutoff. o to step 4. 4) Assume NMO is in active region. Compute i from i = K(v V t ) 2. Then, use KVL to compute v. If v > v V t, we are done. Otherwise go to step 5. 5) NMO has to be in ohmic region. ubstitute for i from i = K[2v (v V t ) v 2 ] in KVL. You will get a quadratic equation in v. Find v (one of the two roots of the equation will be unphysical). Check to make sure that v < v V t. ubstitute v in KVL to find i. ECE60L Lecture Notes, pring
6 Example: Consider NMO circuit below with K = 0.25 ma/v 2 and V t = 2 V. Find v o when v i = 0, 6, and 12 V for R = 1 KΩ and V = 12 V. KVL: v = v i V KVL: V = R i + v R v o A) v i = 0 V. From KVL, we get v = v i = 0. As v < V t = 2 V, NMO is in cutoff, i = 0, and v is found from KVL: v i i KVL: v o = v = V R i = 12 V B) v i = 6 V. From KVL, we get v = v i = 6 V. ince v = 6 > V t = 2, NMO is not in cutoff. Assume NMO in active region. Then: i = K(v V t ) 2 = (6 2) 2 = 4 ma KVL: v = V R i = = 8 V ince v = 8 > v V t = 2, NMO is indeed in active region and i = 4 ma and v o = v = 8 V. C) v i = 12 V. From KVL, we get v = 12 V. ince v > V t, NMO is not in cutoff. Assume NMO in active region. Then: i = K(v V t ) 2 = (12 2) 2 = 25 ma KVL: v = V R i = = 13 V ince v = 13 < v V t = 12 2 = 10, NMO is NOT in active region. Assume NMO in ohmic region. Then: i = K[2v (v V t ) v 2 ] = [2v (12 2) v 2 ] i = [20v v 2 ] ubstituting for i in KVL, we get: KVL: V = R i + v 12 = [20v v 2 ] + v v 2 24v + 48 = 0 ECE60L Lecture Notes, pring
7 This is a quadratic equation in v. The two roots are: v = 2.2 V and v = 21.8 V. The second root is not physical as the circuit is powered by a 12 V supply. Therefore, v = 2.2 V. As v = 2.2 < v V t = 10, NMO is indeed in ohmic region with v o = v = 2.2 V and KVL: v = V R i i = , 000 = 9.8 ma Load Line: Operation of NMO circuits can be better understood using the concept of load line. imilar to BJT, load line is basically the line representing KVL in i versus v space. Load line of the example circuit is shown here. Exercise: Mark the Qpoints of the previous example for v i = 0, 6, and 12 V on the load line figure below. Body Effect In deriving NMO (and other MO) i versus v characteristics, we had assumed that the body and source are connected. This is not possible in an integrated chip which has a common body and a large number of MO devices (connection of body to source for all devices means that all sources are connected). The common practice is to attach the body of the chip to the smallest voltage available from the power supply (zero or negative). In this case, the pn junction between the body and source of all devices will be reversed biased. The impact of this to lower threshold voltage for the MO devices slightly and its called the body effect. Body effect can degrade device performance. For analysis here, we will assume that body effect is negligible. ECE60L Lecture Notes, pring
8 pchannel EnhancementType MOFET (PMO) The physical structure of a PMO is identical to a NMO except that the semiconductor types are interchanged, i.e., body and gate are made of ntype material and source and drain are made of ptype material and a ptype channel is formed. As the sign of the charge carriers are reversed, all voltages and currents in a PMO are reversed. By convention, the drain current is flowing out of the drain as is shown. With this, all of the NMO discussion above applies to PMO as long as we multiply all voltages by a minus sign: i B i Cutoff: v > V t, i = 0 for any v Ohmic: v < V t, i = K[2v (v V t ) v 2 ] for v > v V t Active: v < V t, i = K(v V t ) 2 for v < v V t Note that V t is negative for a PMO. Complementary MO (CMO) Complementary MO technology employs MO transistors of both polarites as is shown below. CMO devices are more difficult to fabricate than NMO, but many more powerful circuits are possible with CMO configuration. As such, most of MO circuits today employ CMO configuration and CMO technology is rapildy taking over many applications that were possible only with bipolar devices a few years ago. 2 2 v i 2 i 2 v o 1 1 i 1 1 ECE60L Lecture Notes, pring
9 epletiontype MOFET The depletiontype MOFET has a structure similar to the enhancementtype MOFET with only one important difference; depletiontype MOFET has a physically implanted channel. Thus, a ntype depletiontype MOFET has already a ntype channel between drain and source. When a voltage v is applied to the device, a current i = I flows even for v = 0. (how I = KVt 2.) imilar to NMO, if v is increased, the channel become wider and i increases. However, in a ntype depletiontype MOFET, a negative v can also be applied to the device, which makes the channel smaller and reduces i. As such, negative v depletes the channels from ntype carriers leading to the name depletiontype MOFET. If v is reduced further, at some threshold value V t (which is negative), the channel disappears and i = 0, as is seen in the figure. It should be obvious that a depletiontype MOFET can be operated either in enhancement mode or in depletion mode. ptype depletion MOFET operate similarly to ptype enhancement MOFET expect that V t > 0 for depletion type and V t < 0 for the enhancement type. Figure below shows i versus v of four types of MOFET devices in the active region. Circuit symbols for depletiontype MOFET devices are also shown. B B i i i i ntype epletion MOFET ptype epletion MOFET ECE60L Lecture Notes, pring
10 NMO Inverter and witch The basic NMO inverter circuit is shown; the circuit is very similar to a BJT inverter. This circuit was solved in page 65 for V = 12 and R = 1 kω. We found that if v i = 0 (in fact v i < V t ), NMO will be in cutoff with i = 0 and v o = V. When v i = 12 V, NMO will be in ohmic region with i = 10 ma and v = 2.2 V. Therefore, the circuit is an inverter gate. It can also be used as switch. v i R V i v o There are some important difference between NMO and BJT inverter gates. First, BJT needs a resistor R B. This resistor converts the input voltages into an i B and keep v BE v γ. NMO does not need a resistor between the source and the input voltage as i = 0 and v i = v can be directly applied to the gate. econd, if the input voltage is high, the BJT will go into saturation with v o = v CE = V sat = 0.2 V. In the NMO gate, if the input voltage is high, NMO is in the ohmic region. In this case, v can have any value between 0 and v V t ; the value of v o = v is set by the value of the resistor R. This effect is shown in the transfer function of the inverter gate for two different values of R. Exercise: Compute v o for the above circuit with V = 12 and R = 10 kω when v i = 12 V. ECE60L Lecture Notes, pring
11 CMO Inverter The CMO inverter, the building block of CMO logic gates, is shown below. The low and high states for this circuit correspond to 0 and V, respectively. CMO gates are built on the same chip such that both NMO and PMO have the same threshold voltage V tn = V t, V tp = V t and same K (one needs different channel length and width to get the same K for PMO and NMO). In this case, the CMO will have a symmetric transfer characteristics, i.e., v o = 0.5V when v i = 0.5V as is shown below. This circuit works only if V > 2V t by a comfortable margin. v i = 0 ince v 1 = v i = 0 < V t, NMO will be in cutoff. Therefore, i 1 = 0. But v 2 = v i V = V < V t, thus, PMO will be ON. Recall i versus v characteristic curves of a NMO (page 63), each labeled with a values of V. As v 2 = V is a constant, operating point of PMO will be on one of the curves. But i 1 = i 2 = 0 and the only point that satisfies this condition is v 2 = 0. Note that PMO is NOT in cutoff, it is in ohmic region and acts like a resistor. v 2 = 0 because i 2 = 0. Output voltage can now be found by KVL: v o = V v 2 = V. o, when v i = 0, v o = V. v i = V ince v 1 = v i = V > V t, NMO will be ON. But since v 2 = v i V = 0 > V t, PMO will be in cutoff and i 2 = 0. ince i 1 = i 2, i 1 = 0. ince NMO is on and i 1 = 0, NMO should be in ohmic region with v 1 = 0. Then v o = v 1 = 0. o, when v i = V, v o = 0 v i = 0.5V In this case, v 1 = v i = 0.5V and v 2 = v i V = 0.5V. ince, v 1 > V t and v 2 < V t, both transistors will be ON. Furthermore, as transistors have same threshold voltage, same K, i 1 = i 2, and v 1 = v 2, both transistor will be in the same state (either ohmic or active) and will have identical v : v 1 = v 2. ince v 1 v 2 = V, then v 1 = 0.5V, v 2 = 0.5V, and v o = 0.5V. Note that since V > 2V t, both transistors are in the active region. The transfer function of the CMO inverter is shown below. 2 2 V V o NMO Off PMO Ohmic NMO Active PMO Ohmic v i 2 i 2 v o NMO Active PMO Active 1 1 i 1 NMO Ohmic PMO Active 1 NMO Ohmic PMO Off V i ECE60L Lecture Notes, pring
12 CMO inverter has many advantages compared to the NMO inverter. Its transfer function is much closer to an ideal inverter transfer function. The low and high states are clearly defined (low state of NMO depended on the value of R ). It does not include any resistors and thus takes less area on the chip. Lastly, i 1 = i 2 = 0 for both cases of output being low or high. This means that the gate consumes very little power (theoretically zero) in either state. A nonzero i 1 = i 2, however, flows in the circuit when the gate is transitioning from one state to another as is seen in the figure. The maximum value of i that flows through the gate during the transition can be easily calculated as this maximum current flows when v i = 0.5V and v o = 0.5V. For example, consider the CMO inverter with V = 12 V, V t = 2 V, and K = 0.25 ma/v 2. Maximum i flows when v i = v 1 = 0.5V = 6 V. At this point, v 1 = v o = 0.5V = 6 V. As, v 1 = 6 > v 1 v t = 4 V, NMO is in active regime. Then: i 1 = K(v 1 V t ) 2 = (6 2) 2 = 4 ma ECE60L Lecture Notes, pring
13 CMO NAN ate As mentioned before CMO logic gates have low and high states of 0 and V, respectively. We need to consider all possible cases to show that this a NAN gate. To start, we can several general observations: 1) by KVL v 1 = v 1, v 2 = v 2 v 1, v 3 = v 1 V, and v 4 = v 2 V, 2) by KCL i 1 = i 2 = i 3 + i 4 v 2 v 1 M 3 M 4 i 3 M 2 V i 4 i 2 i 1 v o 3) by KVL v o = v 1 + v 2 = V + v 3 and v 3 = v 4. M 1 The procedure to solve/analyze CMO gates are as follows: // A) For a given set of input voltages, use KVLs (similar to 1 above) to find v of all transistors and find which ones are ON or OFF.// B) et i = 0 for all transistors that are OFF. Use KCLs (similar to 2 above) to find i for other transistors.// C) Look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. ) Use KVLs (similar to 3 above) to find v o based on v. v 1 = 0, v 2 = 0 We first find v and state of all transistors by using KVL in no. 1 above. v 1 = v 1 = 0 < V t M1 is OFF i 1 = 0 v 2 = v 2 v 1 = v 1 M2 is? v 3 = v 1 V = V < V t M3 is ON v 4 = v 2 V = V < V t M4 is ON ince i 1 = 0, by KCLs in no. 2 above, i 2 = i 1 = 0 and i 3 + i 4 = i 1 = 0. ince i 0 for both PMO and NMO, the last equation can be only satisfied if i 3 = i 4 = 0. We add the value of i to the table above and look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. v 1 = v 1 = 0 < V t M1 is OFF i 1 = 0 v 2 = v 2 v 1 = v 1 M2 is? i 2 = 0 v 3 = v 1 V = V < V t M3 is ON i 3 = 0 v 3 = 0 v 4 = v 2 V = V < V t M4 is ON i 4 = 0 v 4 = 0 Finally, from KVLs in no. 3. above, we have v o = V + v 3 = V. o, when both inputs are low, the output is HIH. ECE60L Lecture Notes, pring
14 If needed, we can go back and find the state of M2. Assume M2 is ON. This requires v 2 > V t. ince i 2 = 0 and M2 is ON, v 2 = 0 (M2 in Ohmic). From KVLs in no. 3. above, we have v o = v 1 + v 2 = V. This gives v 1 = V and v 2 = v 2 v 1 = V V = 0 < V t, a contradiction of our assumption of M2 being ON. Therefore, M2 should be OFF. v 1 = 0, v 2 = V We first find v and state of all transistors by using KVL in no. 1 above. v 1 = v 1 = 0 < V t M1 is OFF i 1 = 0 v 2 = v 2 v 1 = V v 1 M2 is? v 3 = v 1 V = V < V t M3 is ON v 4 = v 2 V = 0 > V t M4 is OFF i 4 = 0 ince i 1 = 0, by KCLs in no. 2 above, i 2 = i 1 = 0. Also, i 3 + i 4 = i 1 = 0 leading to i 4 = 0. We add the value of i to the table above and look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. v 1 = v 1 = 0 < V t M1 is OFF i 1 = 0 v 2 = v 2 v 1 = V v 1 M2 is? i 2 = 0 v 3 = v 1 V = V < V t M3 is ON i 3 = 0 v 3 = 0 v 4 = v 2 V = 0 > V t M4 is OFF i 4 = 0 Finally, from KVLs in no. 3. above, we have v o = V + v 3 = V. o, when v 1 is LOW and v 2 is HIH, the output is HIH. We can go back and find the state of M2. We will find M2 to be ON (left for students). v 1 = V, v 2 = 0 We first find v and state of all transistors by using KVL in no. 1 above. v 1 = v 1 = V > V t M1 is ON v 2 = v 2 v 1 = v 1 < V t M2 is OFF i 2 = 0 v 3 = v 1 V = 0 > V t M3 is OFF i 3 = 0 v 4 = v 2 V = V < V t M4 is ON In the above, we used the fact that v 1 0. ince i 2 = 0, by KCLs in no. 2 above, i 1 = i 2 = 0. Also, i 3 + i 4 = i 2 = 0 leading to i 4 = 0. We add the value of i to the ECE60L Lecture Notes, pring
15 table above and look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. v 1 = v 1 = V > V t M1 is ON v 2 = v 2 v 1 = v 1 < V t M2 is OFF i 2 = 0 v 2 = 0 v 3 = v 1 V = 0 > V t M3 is OFF i 3 = 0 v 3 = 0 v 4 = v 2 V = V < V t M4 is ON Finally, from KVLs in no. 3. above, we have v o = V + v 3 = V. o, when v 1 is HIH and v 2 is LOW, the output is HIH. v 1 = V, v 2 = V We first find v and state of all transistors by using KVL in no. 1 above. v 1 = v 1 = V > V t M1 is ON v 2 = v 2 v 1 = V v 1 M2 is? v 3 = v 1 V = 0 > V t M3 is OFF i 3 = 0 v 4 = v 2 V = 0 > V t M4 is OFF i 4 = 0 From KCLs in no. 2 above, i 2 = i 1 = i 3 + i 4 = 0. We add the value of i to the table above and look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. v 1 = v 1 = V > V t M1 is ON i 1 = 0 v 1 = 0 v 2 = v 2 v 1 = V v 1 = V > V t M2 is ON i 2 = 0 v 2 = 0 v 3 = v 1 V = 0 > V t M3 is OFF i 3 = 0 v 4 = v 2 V = 0 > V t M4 is OFF i 4 = 0 In the above, we used v 1 = 0 to find the state of M2 leading to v 2 = 0. Finally, from KVLs in no. 3. above, we have v o = v 1 + v 1 = 0. o, when v 1 is HIH and v 2 is HIH, the output is LOW. From the truth table, the output of this gate is LOW only if both input states are HIH. Therefore, this is a NAN gate. ECE60L Lecture Notes, pring
16 CMO NOR ate Exercise: how that this is a NOR gate. M 4 V v 2 M 3 i 4 i 3 v o v 1 i 1 i 2 M 1 M 2 ECE60L Lecture Notes, pring
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