Matched N-Channel JFET Pairs
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1 Matched N-Channel JFET Pairs N// PRODUCT SUMMARY Part Number V GS(off) (V) V (BR)GSS Min (V) g fs Min I G Typ (pa) V GS V GS Max (mv) N. to 7. N. to 7. N. to 7. FEATURES BENEFITS APPLICATIONS Two-Chip Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: pa Low Noise: nv Hz Good CMRR: 7 db Minimum Parasitics Tight Differential Match vs. Current Improved Op Amp Speed, Settling Time Accuracy Minimum Input Error/Trimming Requirement Insignificant Signal Loss/Error Voltage High System Sensitivity Minimum Error with Large Input Signals Maximum High Frequency Performance Wideband Differential Amps High-Speed, Temp-Compensated, Single-Ended Input Amps High-Speed Comparators Impedance Converters Matched Switches DESCRIPTION The N// are matched pairs of JFETs mounted in a TO-7 package. This two-chip design reduces parasitics for good performance at high frequency while ensuring extremely tight matching. This series features high breakdown voltage (V (BR)DSS typically > V), high gain (typically > 9 ms), and < mv offset between the two die. The hermetically-sealed TO-7 package is available with full military processing (see Military Information). For similar products see the low-noise U/SST series, and the low-leakage N9/97/98/99 data sheets. TO-7 S G D D G S Top View ABSOLUTE MAXIMUM RATINGS Gate-Drain, Gate-Source Voltage V Gate-Gate Voltage V Gate Current ma Lead Temperature ( / from case for sec.) C Storage Temperature to C Document Number: 7 S- Rev. E, -Jan- Operating Junction Temperature to C Power Dissipation : Per Side a mw Total b mw Notes a. Derate. mw/ C above C b. Derate. mw/ C above C
2 N// SPECIFICATIONS ( UNLESS OTHERWISE NOTED) Static Limits N N N Parameter Symbol Test Conditions Typ a Min Max Min Max Min Max Unit Gate-Source Breakdown Voltage Gate-Source Cutoff Voltage V (BR)GSS I G = A, V DS = V V GS(off) V DS = V, I D = na... Saturation Drain Current b I DSS V DS = V, V GS = V ma Gate Reverse Current I GSS T A = C na V GS = V, V DS = V pa Gate Operating Current c I G na V DG = V, I D = ma pa Drain-Source On-Resistance r DS(on) V GS = V, I D = ma Gate-Source Voltage c V GS V DG = V, I D = ma. Gate-Source Forward Voltage Dynamic Forward Transconductance Output Conductance V GS(F) I G = ma, V DS = V.7 g fs g os V DS = V, I D = ma f = khz V Forward Transconductance d g DS = V, I D = ma fs f = MHz C Input Capacitance iss V DS = V, I D = ma f = MHz Reverse Transfer C rss Capacitance Equivalent Input Noise Voltage e n V DS = V, I D = ma f = Hz ms S ms. Noise Figure NF R G = M db Matching Differential Gate-Source Voltage Gate-Source Voltage Differential Change with Temperature V GS V GS V DG = V, I D = ma mv V GS V GS T V DG = V, I D = ma T A = to C V V pf nv Hz V/ C Saturation Drain Current Ratio c I DSS I DSS V DS = V, V GS = V Transconductance Ratio g fs g fs V DS = V, I D = ma f = khz Common Mode Rejection Ratio c CMRR V DG = to V I D = ma 7 db Notes a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. NCBD b. Pulse test: PW s duty cycle %. c. This parameter not registered with JEDEC. d. Not a production test. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 7 S- Rev. E, -Jan-
3 N// TYPICAL CHARACTERISTICS ( UNLESS OTHERWISE NOTED) rds(on) Drain-Source On-Resistance ( ) rds(on) Drain-Source On-Resistance ( ) gfs Forward Transconductance 8 8 On-Resistance and Drain Current vs. Gate-Source Cutoff Voltage r ID = ma, V GS = I V DS = V, V GS = r DS I DSS 8 V GS(off) Gate-Source Cutoff Voltage (V) Forward Transconductance and Output Conductance vs. Gate-Source Cutoff Voltage g fs and g V DS = V V GS = V, f = khz On-Resistance vs. Temperature I D = ma r DS changes.7%/ C 8 T A Temperature ( C) g fs g os 8 I DSS Saturation Drain Current (ma) gos Output Conductance ( S) rds(on) Drain-Source On-Resistance ( ) Switching Time (ns) Switching Time (ns) 8 8 On-Resistance vs. Drain Current t r t I D = ma Turn-On Switching t r approximately independent of I D V DG = V, R G = V GS(L) = V t I D = ma 8 V GS(off) Gate-Source Cutoff Voltage (V) t d(off) Turn-Off Switching t d(off) independent of device V GS(off) V DG = V, V GS(L) = V t f 8 8 V GS(off) Gate-Source Cutoff Voltage (V) Document Number: 7 S- Rev. E, -Jan-
4 N// TYPICAL CHARACTERISTICS ( UNLESS OTHERWISE NOTED) Drain Current (ma) I D 8 V GS(off) =. V Output Characteristics.7 V 8 V DS Drain-Source Voltage (V) V GS = V. V. V. V. V. V. V Drain Current (ma) I D 8 C C Transfer Characteristics T A = C V DS = V..8.. V GS Gate-Source Voltage (V) Output Characteristics V GS = V V GS(off) =. V. V. V. V Capacitance vs. Gate-Source Voltage f = MHz V DS = V Drain Current (ma) I D. V. V. V.7 V.8 V Capacitance (pf) 8 C iss C rss.9 V V DS Drain-Source Voltage (V) V GS Gate-Source Voltage (V) na na Gate Leakage Current I C I D = ma Common-Gate Input Admittance V DG = V I D = ma g ig I G Gate Leakage pa pa ma ma ma I C b ig pa. pa I I D 8 V DG Drain-Gate Voltage (V). Document Number: 7 S- Rev. E, -Jan-
5 N// TYPICAL CHARACTERISTICS ( UNLESS OTHERWISE NOTED) Common-Gate Forward Admittance V DG = V I D = ma Common-Gate Reverse Admittance V DG = V I D = ma g fg b fg b rg g fg g rg +g rg... Common-Gate Output Admittance V DG = V I D = ma b og g og en Noise Voltage nv / Hz Noise Voltage vs. Frequency V DS = V I D = ma I D = ma. k k k f Frequency (Hz) Output Conductance vs. Drain Current V DS = V f = khz Transconductance vs. Drain Current V DS = V f = khz g os Output Conductance (µs) C T A = C C g fs Forward Transconductance C C T A = C.... maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see Document Number: 7 S- Rev. E, -Jan-
6 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, Vishay ), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 9 Revision: 8-Jul-8
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