# Digital Electronics Part II - Circuits

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1 Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors

2 ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The construction of an NMOS inverter from an n-channel field effect transistor (FET) is described CMOS logic is then introduced Solving Non-linear circuits First of all we need to introduce Ohm s Law. For a linear component such as a resistor, this states that the voltage (V) across the device is proportional to the current () through it, i.e., V = R We will apply this concept to a simple circuit consisting of 2 resistors in series connected across an ideal voltage source known as a potential divider 2

3 V R R 2 Potential Divider What is the voltage at point x relative to the point? V x V 2 V V V 2 V R V2 R2 V R R2 ( R R2 ) V ( R R2) V R2 V2 R2 V ( R R2 ) R R V x 2 Potential Divider How can we do this graphically? V Current through R 2 (2W) R R 2 V x V 2 So if V =, R = W and R 2 = 2W V x R V R R Current through R (W) 6.7V Voltage across R 2 x=6.7v Voltage V= across R 3

4 Graphical Approach Clearly approach works for a linear circuit. How could we apply this if we have a nonlinear device, e.g., a transistor in place of R 2? What we do is substitute the V- characteristic of the non-linear device in place of the linear characteristic (a straight line due to Ohm s Law) used previously for R 2 Graphical Approach V R Device V x V 2 So if V = and R = W The voltage at x is av as shown in the graph Current through Device Device characteristic Current through R (W) Voltage across Device x=av Voltage V= across R 4

5 n-channel MOSFET We will begin by assuming that the Device is a so called n-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Drain (D) The current flow from D to S ( DS ) is controlled by the voltage applied between G and S (V GS ) Gate (G) Source (S) We will be describing enhancement mode devices in which no current flows ( DS =0, i.e., the transistor is Off) when V GS = Diode To help us to understand the operation of the MOSFET, we will consider the operation of a more simple 2 terminal device known as a diode A diode is formed by the junction of so called n-type and p-type silicon () p-type n-type anode cathode 5

6 crystalline lattice poor conductor at low temperatures Semiconductors licon (, Group V) is a poor conductor of electricity, i.e., a semiconductor Shared valence electron is tetravalent, i.e., it has 4 electrons in its valance band crystals held together by covalent bonding Recall that 8 valence electrons yield a stable state each atom now appears to have 8 electrons, though in fact each atom only has a half share in them. Note this is a much more stable state than is the exclusive possession of 4 valence electrons Semiconductors As temperature rises conductivity rises As temperature rises, thermal vibration of the atoms causes bonds to break: electrons are free to wander around the crystal. Hole Free electron When an electron breaks free (i.e., moves into the conduction band it leaves behind a hole or absence of negative charge in the lattice The hole can appear to move if it is filled by an electron from an adjacent atom The availability of free electrons makes a conductor (a poor one) 6

7 n-type n-type silicon (Group V) is doped with arsenic (Group V) that has an additional electron that is not involved in the bonds to the neighbouring atoms As + Free electron The additional electron needs only a little energy to move into the conduction band. This electron is free to move around the lattice Owing to its negative charge, the resulting semiconductor is known as n- type Arsenic is known as a donor since it donates an electron p-type p-type silicon (Group V) is doped with boron (B, Group ) B - Free hole The B atom has only 3 valence electrons, it accepts an extra electron from one of the adjacent atoms to complete its covalent bonds This leaves a hole (i.e., absence of a valence electron) in the lattice This hole is free to move in the lattice actually it is the electrons that do the shifting, but the result is that the hole is shuffled from atom to atom. The free hole has a positive charge, hence this semiconductor is p-type B is known as an acceptor 7

8 Diode When the voltage on the anode rises above the voltage on the cathode, the diode is said to be forward biased, and current flows through the diode from anode to cathode, i.e., electrons flow from n-type region into p-type region since they are attracted to the positive potential at the anode. milarly holes flow from p to n region + p-type n-type anode cathode Diode When the voltage on the anode is below the voltage on the cathode, the diode is said to be reverse biased, and no current flows through the diode + p-type n-type anode cathode 8

9 Diode deal Characteristic d + V d p-type n-type anode cathode d reverse bias 0 0.6V V d forward bias n-channel MOSFET OFF +V D licon dioxide insulator Drain (and Source) diode reverse biased, so no path for current to flow from S to D, i.e., the transistor is off D G S n+ n+ p-type Reverse biased p-n junctions 9

10 n-channel MOSFET ON +V D +V G D G S n+ n+ p-type licon dioxide insulator n-type layer: inversion Consider the situation when the Gate (G) voltage (V G ) is raised to a positive voltage, say V D Electrons attracted to underside of the G, so this region is inverted and becomes n-type. This region is known as the channel There is now a continuous path from n- type S to n-type D, so electrons can flow from S to D, i.e., the transistor is on The G voltage (V G ) needed for this to occur is known as the threshold voltage (V t ). Typically 0.3 to 0.7 V. p-channel MOSFET Two varieties, namely p and n channel p-channel have the opposite construction, i.e., n- type substrate and p-type S and D regions licon dioxide insulator licon dioxide insulator D G S p+ p+ n-type Reverse biased p-n junctions D S G p+ p+ n-type p-type layer: inversion +V S OFF +V S ON 0

11 n-mosfet Characteristics Plots V- characteristics of the device for various Gate voltages (V GS ) At a constant value of V DS, we can also see that DS is a function of the Gate voltage, V GS The transistor begins to conduct when the Gate voltage, V GS, reaches the Threshold voltage: V T n-mos nverter V DD = R =kw V in V GS V V out V DS We can use the graphical approach to determine the relationship between V in and V out Resistor characteristic Note V in =V GS and V out =V DS

12 n-mos nverter Note it does not have the ideal characteristic that we would like from an inverter function Actual deal However if we specify suitable voltage thresholds, we can achieve a binary action. n-mos nverter Actual So if we say: voltage > 9V is logic voltage < 2V is logic 0 The gate will work as follows: V in > 9V then V out < 2V and if V in < 2V then V out > 9V 2

13 n-mos Logic t is possible (and was done in the early days) to build other logic functions, e.g., NOR and NAND using n-mos transistors However, n-mos logic has fundamental problems: Speed of operation Power consumption n-mos Logic One of the main speed limitations is due to stray capacitance owing to the metal track used to connect gate inputs and outputs. This has a finite capacitance to ground We modify the circuit model to include this stray capacitance C R =kw V V DD = V in V GS C C V out 3

14 n-mos Logic To see the effect of this stray capacitance we will consider what happens when the transistor is OFF and then turns ON When the transistor is OFF it is effectively an open circuit, i.e., we can eliminate if from the circuit diagram V DD = Transistor OFF R =kw V C V out The problem with capacitors is that the voltage across them cannot change instantaneously. The stray capacitor C charges through R. V DD = n-mos Logic So what happens to the output voltage V out? We will assume that C is initially contains zero charge, i.e., V out = R =kw Differentiate wrt t gives d 0 R dt C V C V out The capacitor C charges through R. V V Now, V Vout 0 V DD DD V out Q V Then rearranging gives out C V DD R C dt CR and Q dt dt d 4

15 n-mos Logic ntegrating both sides of the previous equation gives t CR a ln We now need to find the integration constant a. To do this we look at the initial conditions at t = 0, i.e., V out =0. This gives an initial current 0 =V DD /R V a ln 0 ln R DD So, t CR t CR ln ln 0 0 Antilog both sides, e t CR 0 e 0 t CR ln n-mos Logic Now, V out and, V out out V V DD DD DD V V R Substituting for V gives, V V R V out V DD R 0 e Substituting for 0 gives, V R R t CR DD e t CR V out V DD Plotting yields, V out V DD 0.63V DD e t CR 0 CR CR is knows as the time constant has units of seconds t 5

16 Transistor ON n-mos Logic When the transistor is ON it is effectively a low value resistor, R ON. (say < 00W) We will assume capacitor is charged to a voltage V DD just before the transistor is turned ON R ON C V out The expression for V out is, t V V out Plotting yields, V out DD e CR ON Stray capacitor C discharges through R ON V DD 0.37V DD 0 CR ON t n-mos Logic When the transistor turns OFF, C charges through R. This means the rising edge is slow since it is defined by the large time constant R C (since R is high). When the transistor turns ON, C discharges through it, i.e., effectively resistance R ON. The speed of the falling edge is faster since the transistor ON resistance (R ON ) is low. V out V DD Transistor OFF Transistor ON 0 Time constant CR Time constant CR ON t CR >CR ON 6

17 n-mos Logic Power consumption is also a problem V DD = R =kw V in V GS V V out V DS Transistor OFF No problem since no current is flowing through R, i.e., V out = Transistor ON This is a problem since current is flowing through R. For example, if V out = V (corresponds with V in = and D = = 9mA), the power dissipated in the resistor is the product of voltage across it and the current through it, i.e., P disp 3 V mW CMOS Logic To overcome these problems, complementary MOS (CMOS) logic was developed As the name implies it uses p-channel as well as n-channel MOS transistors Essentially, p-mos transistors are n-mos transistors but with all the polarities reversed! 7

18 CMOS nverter V in p- MOS n- MOS V out V SS = Using the graphical approach we can show that the switching characteristics are now much better than for the n-mos inverter V in N- MOS P- MOS V out low off on high high on off low CMOS nverter t can be shown that the transistors only dissipate power while they are switching. This is when both transistors are on. When one or the other is off, the power dissipation is zero CMOS is also better at driving capacitive loads since it has active transistors on both rising and falling edges 8

19 CMOS Gates CMOS can also be used to build NAND and NOR gates They have similar electrical properties to the CMOS inverter CMOS NAND Gate 9

20 Logic Families NMOS compact, slow, cheap, obsolete CMOS Older families slow (4000 series about 60ns), but new ones (74AC) much faster (3ns). 74HC series popular TTL Uses bipolar transistors. Known as 74 series. Note that most 74 series devices are now available in CMOS. Older versions slow (LS about 6ns), newer ones faster (AS about 2ns) ECL High speed, but high power consumption Logic Families Best to stick with the particular family which has the best performance, power consumption cost trade-off for the required purpose t is possible to mix logic families and sub-families, but care is required regarding the acceptable logic voltage levels and gate current handling capabilities 20

21 Meaning of Voltage Levels As we have seen, the relationship between the input voltage to a gate and the output voltage depends upon the particular implementation technology Essentially, the signals between outputs and inputs are analogue and so are susceptible to corruption by additive noise, e.g., due to cross talk from signals in adjacent wires What we need is a method for quantifying the tolerance of a particular logic to noise Noise Margin Tolerance to noise is quantified in terms of the noise margin supply voltage (V DD ) Logic (High) noise margin worst case output voltage,v OH (min) worst case input voltage,v H (min) Logic 0 (Low) noise margin Logic 0 noise margin = V L (max) - V OL (max) Logic noise margin = V OH (min) - V H (min) worst case input voltage,v L (max) worst case output voltage,v OL (max) 2

22 Noise Margin For the 74 series High Speed CMOS (HCMOS) used in the hardware labs (using the values from the data sheet): Logic 0 noise margin = V L (max) - V OL (max) Logic 0 noise margin = =.25 V Logic noise margin = V OH (min) - V H (min) Logic noise margin = =.25 V See the worst case noise margin =.25V, which is much greater than the 0.4 V typical of TTL series devices. Consequently HCMOS devices can tolerate more noise pickup before performance becomes compromised 22

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