# Figure 1: MOSFET symbols.

Size: px
Start display at page:

Transcription

1 c Copyright W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between the gate and the channel, the metal-oxide semiconductor FET or MOSFET differs primarily in that it has an oxide insulating layer separating the gate and the channel. The circuit symbols are shown in Fig. 1. Each device has gate (G), drain (D), and source (S) terminals. Four of the symbols show an additional terminal called the body (B) which is not normally used as an input or an output. It connec to the drain-source channel through a diode junction. In discrete MOSFETs, the body lead is connected internally to the source. When this is the case, it is omitted on the symbol as shown in four of the MOSFET symbols. In integrated-circuit MOSFETs, the body usually connec to a dc power supply rail which reverse biases the body-channel junction. In the latter case, the so-called body effect must be accounted for when analyzing the circuit. Figure 1: MOSFET symbols. Device Equations The discussion here applies to the n-channel MOSFET. The equations apply to the p-channel device if the subscrip for the voltage between any two of the device terminals are reversed, e.g. v GS becomes v SG. The n-channel MOSFET is biased in the active mode or saturation region for v DS v GS v TH,where v TH is the threshold voltage. This voltage is negative for the depletion-mode device and positive for the enhancement-mode device. It is a function of the body-source voltage and is given by hp v TH V TO + γ φ vbs p i φ (1) where V TO is the value of v TH with v BS 0, γ is the body threshold parameter, φ is the surface potential, and v BS is the body-source voltage. The drain current is given by i D k0 2 W L (1 + λv DS)(v GS v TH ) 2 (2) where W is the channel width, L is the channel length, λ is the channel-length modulation parameter, and k 0 is given by k 0 µ 0 C ox µ ox t ox 1

2 In this equation, µ 0 is the average carrier mobility, C ox is the gate oxide capacitance per unity area, ox is the permittivity of the oxide layer, and t ox is i thickness. It is convenient to define a transconductance coefficient K given by K k 0 W 2 L (1 + λv DS) K 0 (1 + λv DS ) (3) where K 0 is given by K 0 k 0 W (4) 2 L With these definitions, the drain current can be written i D K (v GS v TH ) 2 (5) Note that K plays the same role in the MOSFET drain current equation as β plays in the JFET drain current equation. Some tex define K k 0 (W/L)(1+λv DS ) so that i D is written i D (K/2) (v GS v TH ) 2.Inthiscase, the numerical value of K is twice the value used here. To modify the equations given here to conform to this usage, replace K in any equation given here with K/2. Transfer and Output Characteristics The transfer characteristics are a plot of the drain current i D as a function of the gate-to-source voltage v GS with the drain-to-source voltage v DS held constant. Fig. 2 shows the typical transfer characteristics for a zero body-to-source voltage. In this case, the threshold voltage is a constant, i.e. v TH V TO. For v GS V TO, the drain current is zero. For v GS >V TO, Eq. (5) shows that the drain current increases as the square of the gate-to-source voltage. The slope of the curve represen the small-signal transconductance g m, which is definedinthefollowing. Figure 2: Drain current i D versus gate-to-source voltage v GS for constant drain-to-source voltage v DS. The output characteristics are a plot the drain current i D as a function of the drain-to-source voltage v DS with the gate-to-source voltage v GS and the body-to-source voltage v BS held constant. Fig. 3 shows the typical output characteristics for several values of gate-to-source voltage v GS. The dashed line divides the triode region from the saturation or active region. In the saturation region, the slope of the curves represen the reciprocal of the small-signal drain-source resistance r 0, which is definedinthenexection. Small-Signal Models There are two small-signal circuit models which are commonly used to analyze MOSFET circui. These are the hybrid-π model and the T model. The two models are equivalent and give identical resul. They are described below. In addition, a simplified small-model is derived which is called the source equivalent circuit. The models are first developed for the case of no body effectandthenwiththebodyeffect. The former 2

3 Figure 3: Drain current i D versus drain-to-source voltage v DS for constant gate-to-source voltage v GS. case assumes that the body-source voltage is zero, i.e. v BS 0. This is the case with discrete MOSFETs in which the source is connected physically to the body. It also applies to small-signal ac analyses for which the body and source leads are connected to the same or different dc voltages. In this case, the small-signal body-source voltage is zero, i.e. v bs 0,andthereisnobodyeffect. No Body Effect The small-signal models in this section assume that the body lead is connected to the source lead. The models also apply when the body and source leads are connected to different dc voltages so that the ac or signal voltage from body to source is zero. Hybrid-π Model Consider the case where the body-source voltage is zero, i.e. v BS 0. In this case, the threshold voltage in Eq. 1 is a constant and given by v TH V TO. Let the drain current and each voltage be written as the sum of a dc component and a small-signal ac component as follows: i D I D + i d (6) v GS V GS + v gs (7) v DS V DS + v ds (8) Iftheaccomponenaresufficiently small, we can write i d I D v gs + I D v ds (9) V GS V DS where the derivatives are evaluated at the dc bias values. Let us define ID r 0 g m I D V GS K (V GS V TH )2 p KI D (10) V DS 1 k0 2 It follows that the small-signal drain current can be written 1 W L λ (V GS V TH ) 2 1/λ + V DS (11) I D i d i 0 d + v ds (12) r 0 where i 0 d g m v gs (13) The small-signal circuit which models these equations is given in Fig. 4. This is called the hybrid-π model. 3

4 Figure 4: π model of the MOSFET. TModel The T model of the MOSFET is shown in Fig. 5. The resistor r 0 is given by Eq. (11). The resistor r s is given by r s 1 (14) g m where g m is the transconductance definedineq.(10).thecurrenaregivenby i d i 0 s + v ds r 0 (15) i 0 s v gs g m v gs (16) r s The curren in the T model are the same as for the hybrid-π model. Therefore, the two models are equivalent. Note that the gate and body curren in Fig. 5 are zero because the controlled source supplies the current that flows through r s. Figure 5: A Source Equivalnet Circuit Figure 6 shows the MOSFET T model described above with a Thévenin source in series with the gate. We wish to solve for the equivalent circuit in which the source i 0 d is replaced by a single source which connec from the drain node to ground having the value i 0 d i0 s. We call this the source equivalent circuit. Looking up into the branch labeled i 0 s,wecanwritev s v tg i 0 sr s With v tg 0,theresistancer s seen looking up into the branch labeled i 0 s is given by r s 1 (17) g m The source equivalent circuit is shown in Fig.7. Note that there is no R tg in the circuit because there is no current through R tg in the original circuit. Compared to the corresponding circuit for the BJT, the MOSFET circuit replaces v tb with v tg and re 0 with r s. Because the gate current is zero, set α 1and β in converting any BJT formulas to corresponding MOSFET formulas. 4

5 Figure 6: Figure 7: With Body Effect The small-signal models in this section assume that the body lead is connected to ac signal ground. In integrated circuit design, this ac signal ground is typically a dc power supply rail. In this case, any ac signal voltage on the source lead causes an ac signal voltage between the body and source. The effect of this voltage is called the body effect. Hybrid-π Model Let the drain current and each voltage be written as the sum of a dc component and a small-signal ac component as follows: i D I D + i d (18) v GS V GS + v gs (19) v BS V BS + v bs (20) v DS V DS + v ds (21) Iftheaccomponenaresufficiently small, we can write i d I D v gs + I D v bs + I D v ds (22) V GS V BS V DS where the derivatives are evaluated at the dc bias values. Let us define g m I D K (V GS V TH )2 p KI D V GS (23) g mb I D γ KID χg m V BS φ VBS (24) χ γ 2 φ V BS (25) 5

6 1 ID k0 r 0 V DS 2 The small-signal drain current can thus be written 1 W L λ (V GS V TH ) 2 V DS +1/λ (26) I D i d i dg + i db + v ds r 0 (27) where i dg g m v gs (28) i db g mb v bs (29) The small-signal circuit which models these equations is given in Fig. 8. This is called the hybrid-π model. If the body (B) lead is connected to the source, then v bs 0and the circuit becomes that given in Fig. 4. Figure 8: Hybrid-π model of the MOSFET. TModel The T model of the MOSFET is shown in Fig. 9. The resistor r 0 is given by Eq. (26). The resistors r s and r sb are given by r s 1 (30) g m r sb 1 1 r s (31) g mb χg m χ where g m and g mb are the transconductances defined in Eqs. (23) and (24). The curren are given by i d i sg + i sb + v ds r 0 (32) i sg v gs g m v gs (33) r s i sb v bs g mb v bs (34) r sb Thecurrenarethesameasforthehybrid-π model. Therefore, the two models are equivalent. Note that the gate and body curren are zero because the two controlled sources supply the curren that flow through r s and r sb. Source Equivalent Circuit Figure 10 shows the MOSFET T model with a Thévenin source in series with the gate and the body connected to signal ground. We wish to solve for the equivalent circuit in which the sources i sg and i sb are replaced by a single source which connec from the drain node to ground having the value i 0 d i0 s. We call this 6

7 Figure 9: T model of the MOSFET. thesourceequivalentcircuit. Thefirstepistolookupintothebranchlabeledi 0 s and form a Thévenin equivalent circuit. With i 0 s 0, we can use voltage division to write r sb r s /χ v s(oc) v tg v tg r s + r sb r s + r s /χ v tg 1+χ (35) With v tg 0,theresistancer 0 s seen looking up into the branch labeled i 0 s is r 0 s r s kr sb r s 1+χ 1 (1 + χ) g m (36) Figure 10: T model with Thévenin source connected to the gate and the body connected to signal ground. The source equivalent circuit is shown in Fig.11. Compared to the corresponding circuit without the body effect, the circuit replaces v tg with v tg / (1 + χ) and r s with r 0 s r s / (1 + χ). To convert the source equivalent circuit with the body effect to one without the body effect, simply set χ 0. The r 0 Approximations No Body Effect The r 0 approximations approximate r 0 as an open circuit except when calculating the resistance seen looking into the drain. Fig. 7 shows the source equivalent circuit for calculating r id v t /i d.theresistorr s is given by r s 1/g m.wecanwrite µ i d i 0 + i s i 0 1 R r s + R v t r 0 + r s kr µ 1 R r e + R (37) 7

8 Figure 11: Source equivalent circuit. It follows that r id is given by r id v µ t r 0 + r s kr i d 1 R / (r s + R ) r 0 1+ R + R (38) r s Figure 12: Circuit for calculating the resistance r id seen looking into the drain. The r 0 approximations for the source equivalent circuit, the hybrid π model, and the T model, respectively, are given Figs. 13 through 15. Because r 0 no longer connec to the source, there is only one source current and i s i 0 s.ifr 0, thenr ic is an open circuit in each. Figure 13: Source equivalnet circuit with r 0 approximations. With Body Effect The r 0 approximations approximate r 0 as an open circuit except when calculating the resistance seen looking into the drain. Fig. 16 shows the source equivalent circuit for calculating r id v t /i d. The resistor rs 0 is given by Eq. (36). We can write µ i d i 0 + i 0 s i 0 1 R rs 0 + R v t r 0 + rskr 0 µ 1 R re 0 + R (39) 8

9 Figure 14: Hybrid π model with the r 0 approximations. Figure 15: T model with the r 0 approximations. It follows that r id is given by r id v t r 0 + r 0 µ skr i d 1 R / (rs 0 + R ) r 0 1+ R rs 0 + R (40) Figure 16: Circuit for calculating the resistance r id seen looking into the collector. The r 0 approximations for the source equivalent circuit, the hybrid π model, and the T model, respectively, are given Figs. 17 through 19. Because r 0 no longer connec to the source, there is only one source current and i s i 0 s.ifr 0, thenr ic is an open circuit in each. Small-Signal High-Frequency Models Figures 20 and 21 show the hybrid-π and T models for the MOSFET with the gate-source capacitance c gs, the source-body capacitance c sb, the drain-body capacitance c db, the drain-gate capacitance c dg,and the gate-body capacitance c gb added. These capacitors model charge storage in the device which affect i high-frequency performance. The first three capacitors are given by c sb c gs 2 3 WLC ox (41) c sb0 (1 + V SB /ψ 0 ) 1/2 (42) 9

10 Figure 17: Source equivalent circuit with r 0 approximations. Figure 18: Hybrid π model with the r 0 approximations. Figure 19: T model with the r 0 approximations. 10

11 c db0 c db (43) (1 + V DB /ψ 0 ) 1/2 where V SB and V DB are dc bias voltages; c sb0 and c db0 are zero-bias values; and ψ 0 is the built-in potential. Capacitors c gd and c gb model parasitic capacitances. For IC devices, c gd is typically in the range of 1 to 10 ff for small devices and c gb is in the range of 0.04 to 0.15 ff per square micron of interconnect. Figure 20: High-frequency hybrid-π model. Figure 21: High-frequency T model. 11

### Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

### Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

### ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

### Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

### 6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

### Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to

### Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

### MOS Transistor Properties Review

MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

### Lecture 11: J-FET and MOSFET

ENE 311 Lecture 11: J-FET and MOSFET FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices.

### Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

### The Gradual Channel Approximation for the MOSFET:

6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

### The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

### ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

### Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

### The Common-Emitter Amplifier

c Copyright 2009. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The Common-Emitter Amplifier Basic Circuit Fig. shows the circuit diagram

### Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

### Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

### ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

### Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

### Chapter 6: Field-Effect Transistors

Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled

### EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

### ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current

### MOS Transistor I-V Characteristics and Parasitics

ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

### MOS Transistor Theory

MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

### Introduction and Background

Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments

### Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

### ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling

ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered

### Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

### MOSFET: Introduction

E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

### Practice 3: Semiconductors

Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

### SOME USEFUL NETWORK THEOREMS

APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem

### Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

### ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

### Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)

Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture

### Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

### ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

### EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

### Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

### Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -

6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large

### Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >

### 5. EXPERIMENT 5. JFET NOISE MEASURE- MENTS

5. EXPERIMENT 5. JFET NOISE MEASURE- MENTS 5.1 Object The objects of this experiment are to measure the spectral density of the noise current output of a JFET, to compare the measured spectral density

### Lecture 4: CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

### Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

### Capacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009

Wilfrid Laurier University June 4, 2009 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists of two conductive

### MOS Capacitors ECE 2204

MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field

### Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers

6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,

### 3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

### EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2

### The Devices. Jan M. Rabaey

The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

### MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

### Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

### MOS Transistor Theory

CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

### EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

### Chapter7. FET Biasing

Chapter7. J configurations Fixed biasing Self biasing & Common Gate Voltage divider MOS configurations Depletion-type Enhancement-type JFET: Fixed Biasing Example 7.1: As shown in the figure, it is the

### ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

### Charge-Storage Elements: Base-Charging Capacitance C b

Charge-Storage Elements: Base-Charging Capacitance C b * Minority electrons are stored in the base -- this charge q NB is a function of the base-emitter voltage * base is still neutral... majority carriers

### EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

### Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

### The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

### Biasing the CE Amplifier

Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

### EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

### CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012

1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET D-FET (Depletion MOS) MOSFET (Enhancement E-FET) DC biasing Small signal

### Metal-oxide-semiconductor field effect transistors (2 lectures)

Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -

### Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter Basics - Outline Announcements. = total current; I D

6.012 - Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter asics - Outline Announcements Handout - Lecture Outline and Summary The MOSFET alpha factor - use definition in lecture,

### MOSFET Capacitance Model

MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small

### EE5311- Digital IC Design

EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM

### CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

### SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

### ELECTRONICS IA 2017 SCHEME

ELECTRONICS IA 2017 SCHEME CONTENTS 1 [ 5 marks ]...4 2...5 a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ]...5 3...6 a. [ 3 marks ]...6 b. [ 3 marks ]...6 4 [ 7 marks ]...7 5...8

### ! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!

### Class 05: Device Physics II

Topics: 1. Introduction 2. NFET Model and Cross Section with Parasitics 3. NFET as a Capacitor 4. Capacitance vs. Voltage Curves 5. NFET as a Capacitor - Band Diagrams at V=0 6. NFET as a Capacitor - Accumulation

### MOSFET Physics: The Long Channel Approximation

MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The

### ECE315 / ECE515 Lecture-2 Date:

Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode

### ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

### EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

### Microelectronics Part 1: Main CMOS circuits design rules

GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

### GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of

### 6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology March 8, 2005 Copyright 2005 by Michael H. Perrott Notation for Mean,

### The Devices: MOS Transistors

The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

### and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

### Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

### 6.012 Electronic Devices and Circuits

Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

### RFIC2017 MO2B-2. A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits

A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits M. Baraani Dastjerdi and H. Krishnaswamy CoSMIC Lab, Columbia University, New

### The Devices. Devices

The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

### ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!

### VLSI Design and Simulation

VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage

### Homework Assignment 08

Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

### ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

### JFET Operating Characteristics: V GS = 0 V 14. JFET Operating Characteristics: V GS = 0 V 15

J Operating Characteristics: V GS = 0 V 14 V GS = 0 and V DS increases from 0 to a more positive voltage: Gate and Source terminals: at the same potential Drain: at positive potential => reverse biased

### Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

### Homework Assignment 09

Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

### Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

### Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

### Chapter 5 MOSFET Theory for Submicron Technology

Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are

### 6.012 Electronic Devices and Circuits

Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

### Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

### Electronic Circuits Summary

Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

### UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm 2 Name: SID: Closed book. Two sheets of notes are