6.012 Electronic Devices and Circuits


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1 Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless otherwise indicated, assume room temperature and that kt/q is V, kt/q ln 10 = 60 mv, and n i = cm 3 for Si. 2. This test is designed so that most parts can be worked independently of the others. 3. All of your answers and any relevant work must appear on these pages. Any additional paper you hand in will not be graded. 4. Make reasonable approximations and assumptions. State and justify any such assumptions and approximations. 5. Be certain that you have all twelve (12) pages of this exam booklet and make certain that you write your name at the top of this page as indicated. 6. You may see your final exam in Room beginning June 5, Grader Use Only PROBLEM 1 (out of 20 possible) PROBLEM 2 PROBLEM 3 PROBLEM 4 (out of 25 possible) (out of 28 possible) (out of 27 possible) TOTAL
2 Problem 1  (20 points) Page 2 of 12 Warmup questions: a) A sample of silicon is known to contain cm 3 arsenic atoms (column V) and 5 x cm 3 boron atoms (column III). What are the thermal equilibrium hole and electron concentrations in this sample at room temperature where n i = cm 3? n o = cm 3 p o = cm 3 b) A high quality long base silicon pn diode is inadvertently irradiated in a nuclear reactor with the consequence that the minority carrier lifetimes on the n and p sides decrease from 104 s to 108 s (no other materials parameters change). How much, if at all, does the diode saturation current change? I ES (after) I ES (before) c) i) Rank order the commonemitter (CE), commonbase (CB), emitter follower (EF) bipolar linear amplifier configurations in order of increasing input resistance, assuming comparable bias levels, I C : Lowest Middle Highest Explanations: ii) Rank order the commonsource (CS), commongate (CG), source follower (SF) MOSFET linear amplifier configurations in order of increasing output resistance, assuming comparable bias levels, I D : Lowest Middle Highest Explanations: Problem 1 continues on the next page.
3 Problem 1 continued Page 3 of 12 d) Answer in five words or less: i) CMOS is one of the fastest MOSFET logic families and it is used in the highest speed microprocessors. At the same time, one of the most important applications for CMOS is in low speed circuitry. What is CMOS's advantage for low speed applications? ii) What major structural change was made to enable the 486 to run faster than the 386 (and again to make the Pentium faster than the 486)? iii) Why is CMOS attractive for linear amplifier applications? Give one reason (there are several). e) A certain commonemitter bipolar transistor amplifier is fabricated using resistors whose resistance is insensitive to temperature and with transistors whose forward current gain, b F, Early voltage, V A, and baseemitter knee voltage, V BE,ON, are essentially unchanged between room temperature (25 C) and 100 C. None the less, when this amplifier is heated to 100 C its voltage gain, A v, drops noticably. Give an explanation as to why the voltage gain might change and use your explanation to estimate A v (100 C)/A v (25 C). A v (100 C)/A v (25 C) End of Problem 1
4 Problem 2  (25 points) Page 4 of 12 The symmetric pn diode shown below, with N Ap = N Nn = cm 3, is illuminated by steady state light that generates M holeelectron pairs/cm 2 s uniformly over the plane at x = 2 w n /3. The p and n region widths, w n and w p, are both 6 µm, and both minority carrier diffusion lengths are much larger than this, i.e., L e, L h >> 6 µm. The electron mobility, µ e, is 1600 cm 2 /Vs, and the hole mobility, µ h, is 600 cm 2 /Vs. Neglect the depletion region widths relative to 6 µm. M Ohmic V AB +  A ptype cm ntype cm B Ohmic w p (6µm) w n (6µm) x a) On the axes below plot the excess minority carrier concentrations throughout the diode when V AB = 0.54 V and M = 0. n'(x), p'(x) w p w n x b) If we take as the criterion for low level injection (LLI) that the excess minority carrier concentration must not exceed 10% of the equilibrium majority carrier concentration, how large can V AB be before LLI is violated when M = 0? V AB c) Now consider setting V AB = 0, i.e., short circuiting the diode, and applying illumination, M = 3.75 x cm 2 s 1. On the axes provided at the top of the next page plot the excess minority carrier concentrations throughout the diode now. Assume p has the value indicated on the axes at x = 2w n /3. Problem 2 continues on the next page.
5 Problem 2 continued Page 5 of 12 n'(x), p'(x) p'(2wn/3) w p d) On the axes below make labeled plots of the hole current density, j H ; the electron current density, j E ; and the total current density, j TOTAL ; throughout the shortcircuited, illuminated device. w n x i) Hole current density: j H w p w n x ii) Electron current density: j E w p w n x iii) Total current density: j TOTAL w p w n x Problem 2 continues on the next page.
6 Problem 2 continued Page 6 of 12 e) i) What is p (2w n /3)? p (2w n /3) = ii) How large can M be before LLI is violated when V AB = 0? M End of Problem 2
7 Problem 3  (28 points) Page 7 of 12 Consider the two silicon device structures shown in crosssection below: Device A: Device B: G G n+ n+ 15 µm 5 µm psi 20 µm psi B B Both of these devices are made on ptype silicon with a net doping level of cm 3, and are 20 µm wide normal to the page. The n + regions are doped to cm 3, and the n + p junction is 1 µm from the top surface. The thin oxide is a high quality thermal oxide 16 nm thick, and covers an area 20 µm wide by 15 µm long. In Device A the n + region is 20 µm wide by 5 µm long and extends just up to the edge of the thin oxide, while in Device B it is 20 µm wide by 20 µm long and extends all the way under the thin oxide, as shown in the figure. You may assume that throughout the silicon the electron mobility, µ e, is 1600 cm 2 /Vs and the hole mobility, µ h, is 600 cm 2 /Vs (except in an inversion layer in which case µ e = 600 cm 2 /Vs and µ h = 400 cm 2 /Vs); that the intrinsic carrier concentration, n i, is cm 3 at room temperature; and that the dielectric constant, e Si, is F/cm. The dielectric constant of the oxide, e ox, is 3 x F/cm, and the electrostatic potential of the gate metal relative to intrinsic Si is 0.3 V. a) i) What is the electrostatic potential of the ptype silicon, relative to intrinisic silicon, in thermal equilibrium at room temperature? Electrostatic potential = ii) What is the builtin potential of the unbiased n+p junction at room temperature? Builtin potential = Problem 3 contines on the next page.
8 Problem 3 continued Page 8 of 12 b) What are the flat band voltages, V FB, of the MOS capacitor structures in Devices A and B, respectively? V FB (Device A) = V FB (Device B) = c ) The magnitude of the threshold voltage, V T, for the MOS structure is 1 V in one of these devices, and 4 V in the other. Use this information and your knowledge of MOS capacitors to deduce the magnitude and sign of V T for each of these MOS capacitors, i.e., the one made on psi and the made on n+si. V T (Device A) = V T (Device B) = d) What is the condition (accumulated, depleted, or inverted) of the semiconductor surface under the thin oxide in each of these devices with a gate voltage, V GB, of 2 Volts? Also give the identity and sheet density of any mobile holes or electrons induced at the oxidesilicon interface. Device A: Device B: Surface condition: Carrier type and sheet concentration: Surface condition: Carrier type and concentration: Problem 3 continues on the next page
9 Problem 3 continued Page 9 of 12 Next consider using these devices as the storage capacitor in the dynamic memory cell illustrated below. The MOSFET is an nchannel device with a threshold voltage, V T, of 0.75 V (ignor any variation with v BS ) and a drain current in saturation of 0.1 (v GS  V T ) 2 ma. A + vab + 2 V nchannel MOSFET G + Device A or B vg  B e) If V GB is initially 0 V and V AB is increased from 0 V to 2 V, what will the new value of V GB be? f) After having been 2 V for a long period of time, V AB is switched to 0 V at t = 0. How will V GB vary with time for t > 0? Give its initial value and describe how it changes with time, if at all. End of Problem 3
10 Problem 4  (27 points) Page 10 of 12 Consider the differential amplifier circuit illustrated below: + 2 V R2 R3 R4 = 6.4 kw IQ4 = 2 ma R1 + vin1  Q1 0 V Q2 + vin2  IBias Q3 CS Q4 + vout W Q5 Q6 Q7 R52 V In this circuit the three nchannel MOSFETs are identical; they have a threshold voltage, V T, of 1 V, a drain current in saturation of 2.5(v GS  V T ) 2 ma, and an Early voltage of 10 V. The MOSFETS do not operate properly if (v GS  V T ) is less than 0.2 V. The npn bipolar junction transistors (BJTs) all have forward betas, b F, of 100, reverse betas, b R, of 5, and an Early voltage of 50 V. The BJT sizes have been adjusted to that to a good approximation you may use V BE,ON = 0.6 V; V CE,SAT = 0.2 V. Assume C S is a short at midband frequencies, and R 2 and R 3 are identical. Note that value of the resistor R 4, the quiescent collector current on Q 4, and minimum quiescent voltage on the gate of Q 3 are indicated on the schematic, as are the supply voltages. a) What must the bias level (I Bias ) on Q 3 be to have a quiescent output voltage of approximately 0 V? (Assume that the quiescent collector current of Q 4 is 2 ma, as indicated, and do not forget its base current.) I Bias = ma Problem 4 continues on the next page
11 Problem 4 continued Page 11 of 12 b) Select R 5 be to be consistent with a quiescent collector current in Q 4 of 2 ma, and a quiescent output voltage of approximately 0 V. R 5 = W c) Select R 1 to give a bias current through Q 5 of 1 ma. You may ignor the base currents of Q 5, Q 6, and Q 7. R 1 = W d) i) In the space below sketch a small signal linear equivalent half circuit one could use to calculate the signal voltage on the gate of Q 3 due to the differencemode input signal, v in1  v in2. Find an expression for this voltage in terms of incremental linear equivalent circuit model parameters. ii) Write an expression for the differentialmode voltage gain of the differential stage (Q 1, Q 2 ) in terms of the resistors, the MOSFET Kfactors, and the quiescent bias levels of Q 1 and Q 2. Select R 2 (= R 3 ) and the drain current of Q 1 and Q 2 to maximize this voltage gain (magnitude). I D = ma, R 2 = Ω, A vd,max = (= R 3 ) Problem 4 continues on the next page
12 Problem 4 continued Page 12 of 12 e) Suppose you can replace R 2 and R 3 with a current mirror made with pchannel MOSFETs with V T = 1 V and V A = 20 V. In the space below draw the schematic of such a current mirror, and discuss what inpact this would have on the voltage gain. f) Looking at the output stage, what are the most positive and negative values of v out possible? Explain your answers. < v out < End of Problem 4 and the Exam.
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