V t vs. N A at Various T ox
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1 V t vs. N A at Various T ox Threshold Voltage, V t T ox = 5.5 nm T ox = 5 nm T ox = 6 nm m = 4.35 ev, Q ox = 0; V sb = 0 V Body Doping, N A (10 17 cm 3 ) X. ZHOU
2 V t vs. T ox at Various N A Threshold Voltage, V t N A = 2x10 17 cm 3 N A = 1x10 17 cm 3 N A = 3x10 17 cm 3 m = 4.35 ev, Q ox = 0; V sb = 0 V Gate Oxide Thickness, T ox (nm) X. ZHOU
3 V t vs. V sb at Various N A and T ox Threshold Voltage, V t N A = 2x10 17 cm 3 ; T ox = 5.5 nm N A = 2x10 17 cm 3 ; T ox = 5 nm N A = 3x10 17 cm 3 ; T ox = 5.5 nm m = 4.35 ev, Q ox = Body Source Voltage, V sb X. ZHOU
4 3D Plot: V t vs. N A and T ox V t (T ox, N A ) 3D Plot 0.9 Threshold Voltage, Vt Body Doping, NA (10 16 cm 3 ) Gate Oxide Thickness, T ox (nm) X. ZHOU
5 Contour Plot: V t vs. N A and T ox X. ZHOU
6 V t0 and V ts vs. L g at V sb = 0 and 2.5 V Threshold Voltage, V t T ox = 5.5 nm, N A = 1.3x10 17 cm 3, X j = 80 nm s = 0.6, d = 0.4 V sb = 2.5 V s = 0.6, d = 0.7 V sb = 0 V V ds = 0.05 V V ds = 2.5 V Gate Length, L g ( m) X. ZHOU
7 V t0 and V ts vs. L g at T ox = 5.5 and 5 nm 0.5 N A = 1.3x10 17 cm 3, X j = 80 nm, V sb = 0 Threshold Voltage, V t T ox = 5 nm T ox = 5.5 nm V ds = 0.05 V V ds = 2.5 V Gate Length, L g ( m) X. ZHOU
8 V t0 and V ts vs. L g at N A = 1.3x10 17 and 8x10 16 cm T ox = 5.5 nm, X j = 80 nm, V sb = 0 Threshold Voltage, V t N A = 1.3x10 17 cm 3 N A = 8x10 16 cm 3 V ds = 0.05 V V ds = 2.5 V Gate Length, L g ( m) X. ZHOU
9 V t0 and V ts vs. L g at Two Pairs of N A and T ox 0.5 X j = 80 nm, V sb = 0 Threshold Voltage, V t T ox = 5 nm T ox = 5.5 nm N N A = 1.3x10 17 cm 3 A = 1.7x10 17 cm 3 V = 0.05 V ds Gate Length, L g ( m) V ds = 2.5 V X. ZHOU
10 V t0 vs. L g for Three X j 0.50 T ox = 5.5 nm, N A = 1.3x10 17 cm 3, V ds = 0.05 V, V sb = 0 Threshold Voltage, V t X j = 80 nm X j = 60 nm X j = 100 nm Gate Length, L g ( m) X. ZHOU
11 V t0 and V ts vs. L g at With and Without Halo Threshold Voltage, V t T ox = 5.5 nm, N A = 1.3x10 17 cm 3, X j = 80 nm, V sb = 0 Halo: = 1.3 = 0.4 m/v 0.25 No Halo V ds = 0.05 V V ds = 2.5 V Gate Length, L g ( m) X. ZHOU
12 I on and I off vs. L g for the Nominal (No Halo) Leakage Current, log(i off ) (A/ m) X j = 80 nm; V dd = 2.5 V 1.5 T ox = 5.5 nm, N A = 1.3x10 17 cm 3 ; = 0, = Gate Length, L g ( m) I off I on Drive Current, I on (ma/ m) X. ZHOU
13 I on and I off vs. L g at New T ox and N A Leakage Current, log(i off ) (A/ m) T ox = 5 nm, N A = 1.7x10 17 cm 3 ; = 0, = X j = 80 nm; V dd = 2.5 V Gate Length, L g ( m) I off I on Drive Current, I on (ma/ m) X. ZHOU
14 I on and I off vs. L g for the Nominal (With Halo) Leakage Current, log(i off ) (A/ m) T ox = 5.5 nm, N A = 1.3x10 17 cm 3 ; = 1.3, = 0.4 m/v X j = 80 nm; V dd = 2.5 V Gate Length, L g ( m) I off I on Drive Current, I on (ma/ m) X. ZHOU
15 I on and I off vs. L g at New T ox and N A with Halo Leakage Current, log(i off ) (A/ m) T ox = 5 nm, N A = 8x10 16 cm 3 ; = 1.3, = 0.4 m/v X j = 80 nm; V dd = 2.5 V Gate Length, L g ( m) I off I on Drive Current, I on (ma/ m) X. ZHOU
16 I off vs. I on at Various L g for Nominal and New T ox and N A Leakage Current, log(i off ) (A/ m) t gox = 30 min, vt = 1.5x10 12 cm 2 T ox = 5.5 nm, N A = 1.3x10 17 cm 3 T ox = 5 nm, N A = 1.7x10 17 cm 3 X j = 80 nm; V dd = 2.5 V L g = 0.25 m Drive Current, I on (ma/ m) Solid: TCAD Open: CM X. ZHOU
17 I ds vs. V gs at L g = 10 m for Parameter Extraction Linear Drain Current, I dlin ( A/ m) T ox = 5.5 nm, N A = 1.3x10 17 cm 3, X j = 80 nm v sat = 10 7 V/cm, E crit = 0.65 MV/cm 0 = 750 cm 2 /Vs, = 1.2; = 0.7 TCAD CM I dlin I dsat Gate Source Voltage, V gs L g = 10 m Saturation Drain Current, I dsat ( A/ m) X. ZHOU
18 Parameter Variation Effect on I dlin vs. V gs at L g = 10 m Linear Drain Current, I dlin ( A/ m) L g = 10 m, T ox = 5.5 nm, N A = 1.3x10 17 cm 3, X j = 80 nm 0 = 750 cm 2 /Vs +/ 20% E crit = 0.65 MV/cm +/ 50% = 1.2 +/ 50% Dotted Line: + Dashed Line: Gate Source Voltage, V gs X. ZHOU
19 Parameter Variation Effect on I dsat vs. V gs at L g = 10 m Saturation Drain Current, I dsat ( A/ m) L g = 10 m, T ox = 5.5 nm, N A = 1.3x10 17 cm 3, X j = 80 nm v sat = 10 7 V/cm, = = 750 cm 2 /Vs +/ 20% E crit = 0.65 MV/cm +/ 50% = 1.2 +/ 50% Dotted Line: + Dashed Line: Gate Source Voltage, V gs X. ZHOU
20 TCAD/CM: I ds vs. V ds at L g = 10 m 40 L g = 10 m Drain Current, I ds ( A/ m) TCAD CM: I dsat CM: I dlin Drain Source Voltage, V ds X. ZHOU
21 TCAD/CM: log(i ds ) vs. V gs at L g = 10 m L g = 10 m Drain Current, I ds (A/ m) Gate Source Voltage, V gs TCAD: I ds (V dd ) TCAD: I ds (V d0 ) CM: I dsat CM: I dlin CM: I dsubs CM: I dsub0 X. ZHOU
22 TCAD/CM: I ds vs. V ds at L g = 0.25 m (Nominal) 1.2 L g = 0.25 m (Old: Nominal) Drain Current, I ds (ma/ m) TCAD CM: I dsat Drain Source Voltage, V ds CM: I dlin X. ZHOU
23 TCAD/CM: log(i ds ) vs. V gs at L g = 0.25 m (Nominal) L g = 0.25 m (Old: Nominal) Drain Current, I ds (A/ m) Gate Source Voltage, V gs TCAD: I ds (V dd ) TCAD: I ds (V d0 ) CM: I dsat CM: I dlin CM: I dsubs CM: I dsub0 X. ZHOU
24 TCAD/CM: I ds vs. V ds at L g = 0.25 m (Split3) 1.2 L g = 0.25 m (New: Split3) Drain Current, I ds (ma/ m) TCAD CM: I dsat Drain Source Voltage, V ds CM: I dlin X. ZHOU
25 TCAD/CM: log(i ds ) vs. V gs at L g = 0.25 m (Split3) L g = 0.25 m (New: Split3) Drain Current, I ds (A/ m) Gate Source Voltage, V gs TCAD: I ds (V dd ) TCAD: I ds (V d0 ) CM: I dsat CM: I dlin CM: I dsubs CM: I dsub0 X. ZHOU
26 V t0 and V ts vs. L g for Old (Nominal) & New (Split3) Wafers 0.6 New: T ox = 5 nm, N A = 8x10 16 cm 3 ; = 1.2, = 0.4 m/v 0.25 Threshold Voltage, V t Old: T ox = 5.5 nm, N A = 1.3x10 17 cm 3 ; = 0, = 0 Symbols: TCAD Lines: CM New (X j = 80 nm, V sb = 0) V ds = 0.05 V Old V ds = 2.5 V Gate Length, L g ( m) X. ZHOU
27 I off vs. I on at Various L g for Old and New Wafers Leakage Current, log(i off ) (A/ m) t gox = 30 ', vt = 1.5, halo = 0 (x10 12 cm 2 ) t gox = 20 ', vt = 0.15, halo = 2 (x10 12 cm 2 ) X j = 80 nm; V dd = 2.5 V L g = 0.25 m T ox = 5.5 nm, N A = 1.3x10 17 cm 3 ; = 0, = 0 T ox = 5 nm, N A = 8x10 16 cm 3 ; = 1.3, = 0.4 m/v Drive Current, I on (ma/ m) Solid: TCAD Open: CM X. ZHOU
28 I ds vs. V ds at L g = 0.25 m for Old and New Wafers 1.2 L g = 0.25 m (old: nominal; new: split3) Drain Current, I ds (ma/ m) Old New TCAD CM (new) CM (old) Drain Source Voltage, V ds I dsat I dlin X. ZHOU
29 log(i ds ) vs. V gs at L g = 0.25 m for Old and New Wafers L g = 0.25 m (old: nominal; new: split3) Drain Current, I ds (A/ m) Symbols: TCAD Lines: Model New Gate Source Voltage, V gs Old I dsat I dlin I dsat I dlin I dsubs I dsub0 X. ZHOU
30 I dlin vs. V gs at L g = 0.25 m for Old and New Wafers Linear Drain Current, I dlin (ma/ m) L g = 0.25 m (V ds = 0.05 V) New: T ox = 5 nm, N A = 8x10 16 cm 3 ; = 1.2, = 0.4 m/v 0.25 Old: T ox = 5.5 nm, N A = 1.3x10 17 cm 3 ; = 0, = 0 (X j = 80 nm, V sb = 0) Symbols: TCAD Lines: CM Solid: Old Open/Dashed: New Gate Source Voltage, V gs X. ZHOU
31 I dsat vs. V gs at L g = 0.25 m for Old and New Wafers Saturation Drain Current, I dsat (ma/ m) L g = 0.25 m (V ds = 0.05 V) Vgs vs idout Vgs vs tcad-iout Vgs vs ids Vgs vs id0 New: T ox = 5 nm, N A = 8x10 16 cm 3 ; = 1.2, = 0.4 m/v 0.25 Old: T ox = 5.5 nm, N A = 1.3x10 17 cm 3 ; = 0, = Gate Source Voltage, V gs (X j = 80 nm, V sb = 0) Symbols: TCAD Lines: CM Solid: Old Open/Dashed: New X. ZHOU
32 Contour Plot (Nominal): I on and I off vs. N A and T ox X. ZHOU
33 Contour Plot (Nominal): I on, I off, and V ts vs. N A and T ox X. ZHOU
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