ESE 570: Digital Integrated Circuits and VLSI Fundamentals
|
|
- Prudence Lawson
- 5 years ago
- Views:
Transcription
1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1
2 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level 1 Model 2
3 MOS Capacitor with External Bias! Three Regions of Operation: " Accumulation Region V G < 0 (Cutoff) " Depletion Region V G > 0, small (Subthreshold) " Inversion Region V G V T, large (Above Threshold) V G V T Cutoff/Subthreshold Above threshold Penn ESE 570 Spring 2018 Khanna 3
4 2terminal MOS Cap # 3terminal nmos VS V G V D depletion region Penn ESE 570 Spring 2018 Khanna 4
5 nmos = MOS cap + source/drain V SB = 0 V S V G V D Penn ESE 570 Spring 2018 Khanna 5
6 Review: Threshold Voltage for V SB = 0 V T =V T 0 = Φ GC Q ox C ox 2Φ F Q B0 C ox for V SB!= 0 V T = V T 0 +γ ( 2Φ F V SB 2Φ ) F γ = 2qN Aε Si C ox Penn ESE 570 Spring 2018 Khanna 6
7 MOSFET IV Characteristics 50 V DS S Drain current [arbitrary unit] Gate to source voltage [V] V GS Penn ESE 570 Spring 2018 Khanna 7
8 MOSFET IV Characteristics V DS <V GS V TH S V GS V th V DS V GS V TH Penn ESE 570 Spring 2018 Khanna V DS 8
9 Cutoff Region V GS < 0 NMOS TRANSISTOR IN CUTOFF REGION V G V D V S Depletion region Substrate or Bulk B p Immobile acceptor ions No depletion or inversion layer under oxide, no current flow 9
10 Depletion Region 0 < V GS < V TH V S V G V D depletion region Depletion layer under oxide, leakage/subthreshold current flow Penn ESE 570 Spring 2018 Khanna 10
11 Onset of Inversion Region V GS = V T0n + δ V DS = 0 V G V D Q I Q B0 Depletion region, and thin inversion layer (aka channel) Thermal equilibrium in channel, leakagelevel current flow 11
12 MOSFET IV Characteristics 50 V DS S Drain current [arbitrary unit] Gate to source voltage [V] V GS Penn ESE 570 Spring 2018 Khanna 12
13 Linear Region V GS > V T0 V DS small, V DS < V GS V T0 n + n + Channel acts like voltage controlled resistor Current flows proportional to V DS ( V DS ) As V D increases, channel depth at the drain decreases 13
14 Channel Voltage! Voltage varies along channel! Channel acts as a resistor " Serves as a voltage divider between V S and V D 14
15 Voltage along Channel! Voltage divider between V S and V D y=0 y=l V(y) y 15
16 Voltage along Channel! Voltage divider between V S and V D V(y) y=0 y=l Vd Vs y 16
17 Voltage along Channel! Voltage divider between V S and V D V(y) y=0 y=l Vd Vs y 17
18 Voltage along Channel! Voltage divider between V S and V D V(y) y=0 y=l Vd Vs y 18
19 Linear/Saturation Region Edge V GS > V T0 V DS = V GS V T0 n + n + Voltage divider along channel, until pinch off As V D increases, channel depth at the drain decreases 19
20 Channel Field! When voltage gap V G V y drops below V th, channel drops out of inversion " If V DS = V GS V th #V GS V DS =V G V D = V th 20
21 Saturation Region V GS > V T0 V DS > V GS V T0 V DS V DSAT V(x) = V DSAT n + z n + 21
22 Channel Field! When voltage gap V G V y drops below V th, drops out of inversion " What if V DS > V GS V th #V DS V GS > V th? " Upper limit on current, channel is pinched off " nmos current saturated 22
23 MOSFET IV Characteristics Linear Region V GS > V T0 V DS small, V DS < V GS V T0 n + z n + 23
24 MOSFET IV Characteristics Linear Region V GS > V T0 V DS small, V DS < V GS V T0 n + z n + V(y) Boundary Conditions: Mobile charge in inverted channel: V(y=0) = V S = 0, V(y=L) = V DS =V D Q I (y) = C ox [V GS V(y) V T0 ] 24
25 MOSFET IV Characteristics Linear Region z x y dr = dy W µ n Q I (y) µ n = electron mobility = cm 2 /(V sec) 25
26 MOSFET IV Characteristics Linear Region Q I (y) = C ox [V GS V(y) V T0 ] dr = dy W µ n Q I (y) Incremental potential drop along the channel segment with width dy dv CS dv C = dr = W µ n Q I (y) dy W µ n Q I (y) dv C = dy 26
27 MOSFET IV Characteristics Linear Region Q I (y) = C ox [V GS V(y) V T0 ] dr = dy W µ n Q I (y) Incremental potential drop along the channel segment with width dy dv CS dv C = dr = W µ n Q I (y) dy W µ n Q I (y) dv C = dy Integrate along the channel: V(y=0) = V S = 0, V(y=L) = V DS L dy = W µ n Q I ( y) dv C 0 V DS L =W µ n C ox 0 V DS 0 (V GS V C V T 0 ) dv C W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 27
28 MOSFET IV Characteristics Linear Region W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ( ' k ' = µ n C ox k = k ' W L = k ' 2 W L 2(V GS V T 0 )V DS V 2 DS ( ) = k ( 2 2(V V )V V 2 GS T 0 DS DS ) 28
29 MOSFET IV Characteristics! Example: For an nmos transistor with μ n = 600cm 2 /Vsec, C ox = 7x10 8 F/cm 2, W = 20μm, L = 2 μm, V T0 = 1V, plot the relationship between and V DS, V GS. 29
30 MOSFET IV Characteristics! Example: For an nmos transistor with μ n = 600cm 2 /Vsec, C ox = 7x10 8 F/cm 2, W = 20μm, L = 2 μm, V T0 = 1V, plot the relationship between and V DS, V GS. W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 = 0.42mA /V 2 (V GS 1.0)V DS V 2 DS 2 30
31 MOSFET IV Characteristics! Example: For an nmos transistor with μ n = 600cm 2 /Vsec, C ox = 7x10 8 F/cm 2, W = 20μm, L = 2 μm, V T0 = 1V, plot the relationship between and V DS, V GS. W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 = 0.42mA /V 2 (V GS 1.0)V DS V 2 DS 2 (V DS = V DSAT ) and V DSAT = V GS V T0 Assumptions: 31
32 MOSFET IV Characteristics W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 V DS =V DSAT =V GS V T 0 W = µ n C ox L (V V )(V V ) (V V GS T 0 )2 GS T 0 GS T 0 2 = µ n C ox 2 W L (V GS V T 0 )2 32
33 MOSFET IV Characteristics W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 LINEAR (V DS = V DSAT ) = (sat) SAT V DS =V DSAT =V GS V T 0 W = µ n C ox L (V V )(V V ) (V V GS T 0 )2 GS T 0 GS T 0 2 = µ n C ox 2 W L (V GS V T 0 )2 IN GENERAL (sat) 33
34 MOSFET IV Characteristics Saturation V DSAT V GS > V T0 V DS > V GS V T0 ΔL n + n + SAT = µ n C ox 2 W L' ( V GS V T 0 ) 2 = µ n C ox 2 W $ L& 1 ΔL % L empirically ΔL V DS V DSAT 1 ΔL L 1 λ V DS ' ) ( ( V GS V T 0 ) 2 If λ$v DS <<1, 1 ΔL L 1 λ V DS 1+ λ V DS 34
35 MOSFET IV Characteristics Saturation SAT = µ n C ox 2 W L' ( V GS V T 0 ) 2 = µ C n ox 2 W $ L& 1 ΔL % L emprically ΔL V DS V DSAT 1 ΔL L 1 λ V DS ' ) ( ( V GS V T 0 ) 2 If λ$v DS <<1, 1 ΔL L 1 λ V DS 1+ λ V DS = µ n C ox 2 W ( L V GS V T 0 ) 2 (1+ λ V DS ) 35
36 MOSFET IV Characteristics Linear Region: W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ( ' Saturation Region: = µ n C ox 2 W ( L V V GS T 0) 2 (1+ λ V DS ) λ 0 λ=0 36
37 MOSFET IV Characteristics Linear Region: W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ( ' Saturation Region: = µ n C ox 2 W ( L V V GS T 0) 2 (1+ λ V DS ) V DS = V DSAT λ 0 λ=0 37
38 MOSFET IV Characteristics Linear Region: W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ((1+ λ V DS ) ' Saturation Region: = µ n C ox 2 W ( L V V GS T 0) 2 (1+ λ V DS ) V DS = V DSAT λ 0 λ=0 38
39 MOSFET IV Characteristics Linear Region: W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ((1+ λ V DS ) ' Saturation Region: Level 1 model λ$v DS <<1 = µ n C ox 2 W ( L V V GS T 0) 2 (1+ λ V DS ) V DS = V DSAT λ 0 λ=0 39
40 MOSFET IV Characteristics, V SB 0 V T = V T 0 +γ ( 2Φ F V SB 2Φ ) F Linear Region: W # = µ n C ox L (V GS V T (V SB ))V DS V 2 DS % $ 2 & ((1+ λ V DS ) ' Saturation Region: = µ n C ox 2 W L V GS V T (V SB ) ( ) 2 (1+ λ V DS ) = f (V GS,V DS,V SB ) 40
41 nmos IV Characteristics % ' ' ' = & ' ' ' ( 0 V GS V Tn Cutoff/Subthreshold µ n C ox W ( 2 L 2 ( V GS V Tn (V SB ))V DS V 2 DS )(1+ λ V DS ) V GS > V Tn,V DS < V GS V Tn Linear/Resistive µ n C ox W ( 2 L V GS V Tn (V SB )) 2 (1+ λ V DS ) V GS > V Tn,V DS V GS V Tn Saturation 41
42 pmos IV Characteristics % ' ' ' = & ' ' ' ( 0 V GS V Tp Cutoff/Subthreshold µ p C ox W ( 2 L 2 ( V GS V Tp (V SB ))V DS V 2 DS )(1+ λ V DS ) V GS < V Tp,V DS > V GS V Tp Linear/Resistive µ p C ox W ( 2 L V GS V Tp (V SB )) 2 (1+ λ V DS ) V GS < V Tp,V DS V GS V Tp Saturation 42
43 Measurement of Parameters k n,p D G B S 43
44 Measurement of Parameters k n,p D G B S 44
45 Measurement of Parameters k n,p D G B S 45
46 Measurement of Parameters γ D G S B => SA T 46
47 Measurement of Parameters λ => SAT 47
48 Measurement of Parameters λ => SAT 48
49 Measurement of Parameters λ => SAT 49
50 Subthreshold 50
51 Below Threshold! Transition from insulating to conducting is nonlinear, but not abrupt! Current does flow " But exponentially dependent on V GS 51
52 Below Threshold! Transition from insulating to conducting is nonlinear, but not abrupt! Current does flow " But exponentially dependent on V GS 52
53 Parasitic NPN BJT! We have an NPN sandwich, mobile minority carriers in the P region! This is a BJT! " Except that the base potential is here controlled through a capacitive divider, and not directly an electrode Penn ESE 570 Spring 2018 Khanna 53
54 Subthreshold If V GS < V th, S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( )! Current is from the parasitic NPN BJT transistor when gate is below threshold and there is no conducting channel " n is the capacitive divider between parasitic capacitances " Typically 1 < n < 1.5 n = C js + C ox C ox 54
55 Subthreshold If V GS < V th, S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( )! Current is from the parasitic NPN BJT transistor when gate is below threshold and there is no conducting channel " n is the capacitive divider between parasitic capacitances " Typically 1 < n < 1.5 n = C js + C ox C ox 55
56 Subthreshold! W/L dependence follow from resistor behavior (parallel, series) " Not shown explicitly in text S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( ) 56
57 Subthreshold Slope! Exponent in V GS determines how steep the turnon is " S = n kt % $ ' ln( 10) # q & " Units: V/decade " Every S Volts, S is scaled by factor of 10 S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( ) 57
58 Subthreshold Slope! Exponent in V GS determines how steep the turnon is " S = n kt % $ ' ln( 10) # q & " Units: V/dec " Every S Volts, S is scaled by factor of 10! n depends on parasitic capacitance divider " n=1 # S=60mV at Room Temp. (ideal) " n=1.5 # S=90mV " Single gate structure showing S=90110mV 58
59 S vs. V GS (Logscale) 59
60 S vs. V GS S (Logscale) 60
61 Subthreshold Slope! If S=100mV and V th =300mV, what is Ids(Vgs=300mV)/Ids(Vgs=0V)?! What if S=60mV? " S = n$ kt # q % ' ln 10 & ( ) S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( ) 61
62 Steady State! What current flows in steady state?! What causes (and determines) the magnitude of current flow?! Which device? 62
63 Leakage! Call this steadystate current flow leakage! I ds,leak 63
64 Big Idea! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation " Pinch Off " Channel length modulation! Level 1 Model " =f (V GS, V DS, V SB ) " Empirical measured parameters: k, γ,λ 64
65 Admin! HW 2 due tonight! HW 3 due Thursday, 2/1 " Posted tonight after class " Gets you started with Cadence " Make sure you can setup and launch Cadence tonight or tomorrow " Don t wait until night before homework is due! Penn ESE 570 Spring 2018 Khanna 65
Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 5: Januar 6, 17 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 6, 01 MOS Transistor Basics Today MOS Transistor Topology Threshold Operating Regions Resistive Saturation
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 217 MOS Transistor Theory, MOS Model Lecture Outline! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationFIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 6: January 30, 2018 MOS Operating Regions, pt. 2 Lecture Outline! Operating Regions (review) " Subthreshold " Resistive " Saturation! Intro.
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More information! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)
ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationEE5311- Digital IC Design
EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationLecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationEE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More information6.012 MICROELECTRONIC DEVICES AND CIRCUITS
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6.012 MICROELECTRONIC DEVICES AND CIRCUITS Answers to Exam 2 Spring 2008 Problem 1: Graded by Prof. Fonstad
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationToday s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationChapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationHW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7
HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2 What do digital IC designers need to know? 5 EE4 EECS4 6 3 0< V GS - V T < V DS Pinch-off 7 For (V GS V T )
More informationEE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania
1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationMetal-oxide-semiconductor field effect transistors (2 lectures)
Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationP. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More informationLecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 28-1 Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007 Contents: 1. Second-order and
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More informationMOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor
MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 26, 2019 Energy Optimization & Design Space Exploration Penn ESE 570 Spring 2019 Khanna Lecture Outline! Energy Optimization! Design
More informationCheck course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory
EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday
More informationESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15
ESE 570 MOS TRANSISTOR THEORY Part 1 TwoTerminal MOS Structure 2 GATE Si Oxide interface n n Mass Action Law VB 2 Chemical Periodic Table Donors American Chemical Society (ACS) Acceptors Metalloids 3 Ideal
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University
NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the
More informationECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION
ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors
More informationFundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationCircuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More informationChapter 13 Small-Signal Modeling and Linear Amplification
Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors
More informationECE315 / ECE515 Lecture-2 Date:
Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 6: September 18, 2017 MOS Model You are Here: Transistor Edition! Previously: simple models (0 and 1 st order) " Comfortable
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationLecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)
Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture
More informationLecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
More informationAnnouncements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD
More informationMOSFET Capacitance Model
MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small
More informationNanoscale CMOS Design Issues
Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal
More informationCharge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn )
The Inverted MO Capacitor (V > V Tn ) We consider the surface potential as Þxed (ÒpinnedÓ) at φ s,max = - φ p φ(x).5 V. V V ox Charge torage in the MO tructure Three regions of operation: Accumulation:
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage
More information