# CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS

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1 CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancement-type N-MOS transistor 5.3 I-V characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5 MOS logic circuits 5.6 Some other considerations on MOSFETs 1

2 The ideal two-terminal MOS structure t ox 0 + φ S _ x Q G Q S V G N A P-type silicon M O S V G φ = s Q C t ox - oxide thickness ε ox - permittivity of oxide G ox Charge conservation Q G + Q = φ S - surface potential S V G C ox = = φ C ox - oxide capacitance/unit area Q G (Q S ) - gate (semiconductor) charge/ unit area 0 N A acceptor concentration What s the electric field E ox inside the oxide? s ε t ox ox Q C 2 S ox Potential balance equation

3 The ideal two-terminal MOS structure V G V G = φ s Q C S ox Flat band Q G M ln p, n p N A t ox 0 + φ S Q S O S metal oxide n silicon n 2 i / N A _ x -t ox 0 Carrier concentration along x for φ S =Q S =0 x N A P-type silicon p = N A Reference potential (gnd) n = n 2 i / N A 3

4 The ideal two-terminal MOS structure t ox 0 + φ S _ x Q G Q S V G N A P-type silicon M O S ln p, n metal Carrier concentration along x for φ S >0 (Q S <0) p and n vary along x according to Boltzmann statistics p = p e = N e Reference potential (gnd) oxide -t ox 0 o p n φ / φ t φ / φ t A 2 φ / φ ni φ / φ n = noe t = e N p A = N A V n = n 2 i / N A G = φ t s Q C silicon n S ox N A 2 i / 4 N x A

5 The flat-band voltage (V FB ) The flat-band voltage is the gate-to-bulk voltage required to impose φ S =0 (and Q S =0). When V GB =V FB silicon is neutral everywhere. V = V FB GB φ = Q = 0 s S Why is the flat-band voltage not equal to zero? 1. Charges inside the insulator and at the semiconductor-insulator interface 2. Contact potential between the gate and the semiconductor substrate 5

6 The flat-band voltage (V FB ) The effect of contact potential and oxide charges can be counterbalanced by applying a gate-bulk voltage called the flat-band voltage V FB. V GB = V FB Q S =0 B G p-substrate ln p, n metal The potential balance equation then becomes V oxide -t ox 0 p n Q V = φ C G FB s S ox silicon n 2 i / 6 N A n i x N A

7 Regions of operation of the MOSFET: Accumulation (p-substrate) V GB G Q G Q S p-substrate B V φ Q G B s S < V < 0 > 0 F B Holes + accumulate in the p-type semiconductor surface 7

8 Accumulation (p-substrate) G Q G V GB x Q S p-substrate V φ G B s Q S < V < 0 > 0 F B B p = N e a qφ ( x) kt n = n N 2 qφ ( x) i kt e a 8

9 Regions of operation of the MOSFET: Depletion (p-substrate) V GB G Q o Q G Q S - V φ Q G B s S > < > 0 0 V F B Holes evacuate from the P semiconductor surface and acceptor ion charges become uncovered - B 9

10 Depletion (p-substrate) G Q G n = n N 2 qφ ( x) i kt a e p = N e a qφ ( x) kt V GB Q - - S - p φ s > 0 B n n i 10

11 Regions of operation: Depletion (p-substrate) (depletion approx.) ρ ρ = qn ; 0< x x A =0 ; x> x d d E qn A x d εs qn A E= ( xd x); 0< x x ε s =0 ; x> x d d qn 0 A oxide silicon x d Q qn x = 2 qε N φ = γc φ D A d s A s ox s γ = 2 qε sn A / Cox x oxide dφ qn E = with φ xd = 0 x = xd x dx 2ε s qn A 2 φ ( x = 0) = φs = xd 2ε A ( ) φ ( ) ( ) 2 s 0 silicon φ φ s x d x Body effect factor oxide 0 silicon x d x 11

12 Regions of operation of the MOSFET: Inversion (p-substrate) φ s Q S > φ F < 0 Q G G Many electrons approach the surface! V GB Q o Q S metal ln p, n oxide p n silicon n 2 i / N A n i N A B -t ox 0 When φ = φ p( x = 0) = n( x = 0) = n s F i x 12

13 Regions of operation of the MOSFET - Inversion (p-substrate): φs > φf Φ F is the Fermi potential p = n = N e n N a 2 i a qφ ( x) kt e qφ ( x) kt At this point p=n=n i and φ=φ F n kt N n( φ = φ ) = n = e φ = ln N q n 2 qφf i kt F i F a The semiconductor operates in inversion when φ S >φ F For φ >φ F the concentration of minority carriers (n) at the semiconductor-oxide interface becomes higher than that of majority carriers (p); the semiconductor operates in the inversion region 13 i a

14 Strong inversion : the concentration of minority carriers (n) becomes higher than that of holes (majority carriers) deep in the bulk p = n = N e n N a 2 i a qφ ( x) kt e qφ ( x) kt 2 qφ ni kt N kt a n = Na = e φ = 2 ln = 2φ F N q n a i The semiconductor operates in strong inversion when φ S >2φ F 14

15 Operating regions of the MOSFET: Summary log p, n 0 n p silicon Accumulation N A n i n 2 i / N A x φ < 0; Q > 0 s S log p, n p n 0 Depletion silicon N A n i n 2 i / N A x 0 < φ < φ ; Q < 0 s F S log p, n 0 N A n i log p, n N A n i p p silicon silicon n n n 2 i / N A n 2 i / N A 0 x x Strong inversion Weak inversion φ < φ < 2 φ ; Q < 0 2 φf < φs ; QS < 0 F s F S What is n(x) and p(x) if V GB =V FB? 15

16 Threshold voltage V T ( for strong inversion) Gate voltage for which φ = 2 s φ F V = V V + 2φ + γ 2 φ φ φ T GB = 2 FB F F s F Q qn x = 2 qε N φ = γc 2 φ D A d s A s ox F γ = 2 qε N / C Body effect factor s A ox strong inversion ( ) Q = C V V N ox GB T weak inversion 16

17 Small-signal equivalent circuit of the MOS capacitor in weak inversion C gb dqg dqs dqs 1 = = = = dv dqs d s 1 GB dv φ GB dφs + C dq C V V = φ Q / C GB FB s S ox ox S ox In weak inversion Q N /Q D <<1 V GB C s ( + Q ) dq d Q dq dφ dφ dφ S D N D = = = s s s C d C ox φ s C d : depletion capacitance C d C gb = C C ox d 17

18 Weak inversion model of the MOS device φ s dqd Cox Q γ γc φ C = ( n 1) C dφ 2 φ = D ox s d ox s s depletion region V GB p-type neutral region V GB C ox C d φ s n (slope factor), a dimensionless factor, is a function of φ s, but let us assume it is a constant. d C φ s = ox = GB ox d 1 dv C + C n 1 φ = 2φ + n ( V V ) s F GB T (I) Integrating (I) between φ s and φ s = 2φ F (V GB =V T ) leads to Boltzmann statistics applied to the electron charge density (Q N ) Q N φ s VGB V T exp exp φt nφt Note: The symbol n has been used for both electron concentration and slope factor. 18

19 5.2 The Enhancement-Type NMOS Transistor n + Source Region W S Channel Region B L G n n+ + Drain Region Metal D Silicon Dioxide ( SiO ) 2 P-Type Substrate (Body) 0.8 µ CMOS technology L min = 0.8 µm metal width 1.4 µm Wmin = 2.0 µm t ox = 160 Å X j = 0.40 µm Source (S) v S i i G i S D Gate (G) n + Channel Region n + L v G P-Type Substrate Body (B) v D Drain (D) x j i B ( a ) NMOS transistor structure ( b ) cross section and ( c ) circuit symbol G D i D i G i B i S B v B i G = 0 i B = 0 i D = i S S 19

20 Energy barrier at source controlled by both source and gate voltages Energy barrier at drain controlled by both drain and gate voltages /Silicon%20Valley/Pages/snug-2012-keynote- 3d-finfet.aspx 20

21 1 I = W C V V V V 2 2 ( ) L µ D ox GS T DS DS V GS V T V DS V DSSAT For small V DS : W I C ( V V ) V L µ D ox GS T DS and did = W C ox V GS V T DS dv L µ ( ) 8.00e-4 V = 5 V GS Drain-Source Current (A) 6.00e e e-4 V GS = 4 V V GS = 3 V V = 2 V GS 0.00e Drain-Source Voltage (V) 0.8 NMOS i-v characteristics in the linear region (V SB = 0) 21

22 2.20e e-4 Linear Region V = 5 V GS I D 0 for V GS V T Drain-Source Current (A) 1.80e e e e e e e e e e Pinchoff Locus V GS= 2 V 6 Saturation Region V GS= 4 V V = 3 V GS Drain-Source Voltage (V) 8 V GS= 1 V Output characteristics for an NMOS transistor with V Tn = 1 V and (W/L)µ n C ox = 25 x 10-6 A / V G W 1 I = C V V V V 2 ( ) L µ 2 D ox GS T DS DS V GS V T V DS V DSSAT I = W C V V 2L µ D ( ) 2 D ox GS T I D B V GS V T V DS V DSSAT V D V S S 22

23 MOSFET I-V RELATIONSHIP ,00E-03 1,00E-04 I D (A) SI V D = V G I D V D 1,00E ,00E-06 MI V S = 0 V V G V S 1,00E-07 WI 2.5 1,00E ,00E V G (V) 0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00 4,50E+00 Common-source characteristics 23

24 5.4 The PMOS Transistor Source v v < 0 S G v < 0 D i i S G Gate i D Drain p + Channel Region p + L N-Type Substrate Body i B v > 0 B Cross section of an enhancement-mode PMOS transistor S D S B D I D I D G G 24

25 5.4 The CMOS Technology V (0 V) SS v I V (5 V) DD B p+ Ohmic contact S v o n+ n+ p+ p+ NMOS transistor D D p-type substrate n-well S PMOS transistor B n+ Ohmic contac N-well CMOS structure for forming both NMOS & PMOS transistors in a single silicon substrate 25

26 5.6 MOS logic circuits: the ideal inverter 26

27 MOS logic circuits: the real inverter V IL V IH 27

28 The CMOS Inverter-I S V = 5 V DD V = 5 V DD R onp G D M P v I v O v I D v O G M N (a) S (b) R onn ( a ) CMOS inverter uses one NMOS and one PMOS transistor ( b ) Simplified model for the CMOS logic gate 28

29 The CMOS Inverter-II I Dn V in = 0 V in = 2.5 PMOS V in = 0.5 V in = 2 NMOS V in = 1 V in = 1.5 V in = 1.5 V in = 1 V in = 2 V in = 1.5 V in = 1 V in = 0.5 V in = 2.5 V in = 0 V out 29

30 The CMOS inverter: VTC and dc current O u t p u t V o l t a g e 4.0V 2.0V 1 M off N v = v o I 2 M saturated N M linear P + 1 V IL 3 M and M saturated N P M saturated P M linear N Drain current ( µa ) V v o = v I - 1 V IH 0V 1.0V 2.0V 3.0V 4.0V 5.0V v I 4 5 M off P CMOS voltage transfer characteristic may be broken down into the five regions outlined in table v I ( V ) K n = K p = 50 µa / V 2 V TN = -V TP = 1V P static = V DD i leakage +V DD i sc P short-circuit = V DD i sc 30

31 Impact of Process Variations 2.5 V out (V) Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS V in (V) Process variations are electrically modeled through variations of parameters (V T, k p, k n, etc ) 31

32 Dynamic Operation of the CMOS Inverter -1 V = 5 V DD V = 5 V DD V = 5 V DD v I M P v O v = 5 V I v (0+) = 5V O v I M P v O M P v (0+) = 0V O M N C M N C M N C V = 0 V I C (a) (b) (a) (b) v I v O v I v O + 5V + 5V + 5V + 5V 0 V 0 t 0 V 0 t 0 V 0 t 0 V 0 t High-to-low output transition in a CMOS inverter Low -to- high output transition in a CMOS inverter C: load capacitance + interconnect capacitance + parasitic capacitance of the inverter 32

33 Dynamic Power Dissipation in CMOS Gates - 1 V DD V I M P V I M N v o C v o T What is the energy dissipation for changing v o from 0 to V DD and back to 0? The energy dissipation in M P when v o changes from 0 to V DD is Assumptions: Step v i, constant C The energy stored in C when v o =V DD is E = CV 2 C ( p ) = ( p ) ( p ) = ( DD o ) E M v M i M dt V v dq V DD ( ) ( ) E M == C V v dv = C V 2 2 p DD o o DD 0 2 DD 33

34 Dynamic Power Dissipation in CMOS Gates - 2 V DD V I M P V I M N v o C v o T The energy dissipation in M N when v o changes from V DD to 0 equals the energy stored in the capacitor before discharging it P CV E M v M i M dt v Cdv E C V = T 0 2 DD N = N N = o o = = C 2 V ( ) ( ) ( ) 2 DD P = f 2 C V DD DD When the operation of charging and discharging the capacitor is repeated each T seconds (or f times per second), the power dissipation is In general, the average dynamic power dissipation is 2 P = af C V DD a is the switching activity factor 34

35 CMOS Gates ( Static Logic ) V = 5 V DD V DD 10 1 PMOS Switching Network Logic Inputs Y 10 1 Y NMOS Switching Network A 2 1 B 2 1 C Basic CMOS logic gate structure Two-input CMOS NOR gate 35

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37 The complete I-V relationship of the MOSFET ( strong and weak inversion) ,00E-03 1,00E-04 I D (A) V D = V G VD 1,00E ,00E-06 V S = 0 V V G V S I D 1,00E ,00E ,00E V G (V) 0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00 4,50E+00 Common-source characteristics 37

38 Prof. James Meindl: Theoretically, the minimum supply voltage for a CMOS inverter is 2 (ln2) (kt/q) = 36 mv at room temperature (IEEE JSSC, 2000) 38

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47 Series-parallel association of MOSFETs 47

48 Regenerative Property out out v 3 f (v) v 3 fin v(v) v 1 v 1 fin v(v) v 3 f (v) v 2 v 0 Regenerative in v 0 v 2 Non-Regenerative in 48

49 Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6 A chain of inverters 5 V (Volt) 3 v 0 1 v 1 v 2 Simulated response t (nsec)

50 Ring Oscillator v 0 v 1 v 2 v 3 v 4 v 5 v 0 v 1 v 5 T = 2 t p N 50

51 REFERENCES R. F. Pierret, Field Effect devices, 2 nd ed., Addison-Wesley, Y. Tsividis, Mixed Analog-Digital VLSI Devices and Tecnology, World Scientific,1996. C. Galup-Montoro and M. C. Schneider, MOSFET Modeling for Circuit Analysis and Design, World Scientific, M. C. Schneider and C. Galup-Montoro, CMOS Analog Design Using All- Region MOSFET Modeling, Cambridge, R. Howe, and C. Sodini. Microelectronics: An Integrated Approach. Prentice Hall, J. Rabaey, A. P. Chandrakasan, B. Nikolić, Digital Integrated Circuits: A Design Perspective, Pearson Education, L. A. Pasini Melek, Operação de Circuitos Lógicos CMOS de (ultra)-baixo consumo, Dissertação de mestrado, UFSC,

52 Example: oxide capacitance (a) Calculate the oxide capacitance per unit area for t ox = 5 and 20 nm. The permittivity of silicon oxide is ε ox = 3.9ε 0. ε 0 = F/cm is the permittivity of free space. (b) Determine the area of a 1pF metal-oxide-metal capacitor for the two oxide thicknesses given in (a). (c) Determine the gate charge/unit area in C/cm 2 and the number of elementary charges/µm 2 of the 1 pf capacitor for V G -φ S =1 V Answer: (a) C ox = 690 nf/cm 2 = 6.9 ff/µm 2 for t ox =5 nm and C ox = 172 nf/cm 2 = 1.7 ff/µm 2 for t ox = 20 nm. (b)the capacitor areas are 145 and 580 µm 2 for oxide thicknesses of 5 and 20 nm, respectively. (c) and /µm 2 for capacitor area of 145 µm 2 and and /µm 2 for capacitor area of 580 µm 2. 52

53 Example: charge density z y W t x L Assume that the electron concentration is n = cm -3, L=W=1 um, t=0.1 um (a) Calculate the volumetric charge density (b) Calculate the total number of electrons and the corresponding charge inside the volume (c) Calculate the (areal) charge density seen from the z-direction Answer: (a) ρ= C/cm 3 (b) Number of electrons = 10 3, charge = -1.6 x C (c) charge density Q n = -1.6 x 10-8 C/cm 2. 53

54 The flat-band voltage (V FB ) 1. Charges inside the insulator and at the semiconductorinsulator interface induce a semiconductor charge at zero bias. ρ(x) Q o Q G +Q S +Q o =0 Metal Oxide Silicon Q S QG x V GB =0 V FB G Q o Q G Q - - S B ρ(x) Q o Q G +Q S +Q o =0 Metal Oxide Silicon Q G -t ox Q S =0 0 x V GB =V FB G - - Q- G Qo Q S =0 54 B

55 The flat-band voltage (V FB ) 2. In equilibrium (with the two terminals shortened), the contact potential between the gate and the semiconductor substrate of the MOS induces charges in the gate and the semiconductor for V GB =0. ρ(x) Q G +Q S =0 Metal Oxide Silicon Q G x V GB =0 ρ(x) Q G =Q S =0 Metal Oxide Silicon x V GB =V FB -t ox 0 55

56 Example: flat-band voltage V V (a) Determine the expression for the flat-band voltage of n + polysilicon-gate on p-type silicon (b) Calculate the flat-band voltage for an n + polysilicon-gate on p-type silicon structure with N A = atoms/cm 3. Answer: (a) In equilibrium, by analogy with an n + p junction, the potential of the n + -region is positive with respect to that of the p- region. The flat-band condition is obtained by applying a negative potential to the n + gate with respect to the p-type semiconductor of value (b) N A _ + = φ _ + = 0.56 V φ ln ni FB n p bi n p t FB 7 ( ) = 0.56 V φ ln 10 = 980 mv t G n + gate p-substrate B G n + gate 980 mv p-substrate B 56

57 Example: threshold voltage Estimate V T for an n-channel transistor with n + polysilicon gate, N A =10 17 atoms/cm 3 and t ox =5 nm. Answer: The flat-band voltage (slide 12) is V; φ F =0.419; C ox = 690 nf/cm 2. The body-effect factor is γ = 2 qε N / C = V s A ox V V + 2φ + γ 2 φ = = 0.1V T FB F F For this low value of the threshold voltage, the off-current (for V GS =0) is too high for digital circuits (see subthreshold leakage). Solution to control the magnitude of the threshold voltage a non-uniform high-low channel doping N S N A 57

58 Exact relationship between surface potential and applied gate voltage V G for the MOS capacitor Approximation Strong inversion ( ) Q = C V V N ox GB T Depletion/weak inversion Accumulation Q N VGB V T exp nφt 58

59 Threshold voltage V T ( for strong inversion) Gate voltage for which φ = 2 QS = QN + QD s φ F Q N Q D Electron (carrier) charge Depletion (ion) charge Charge sheet approx. Depletion approx. 2φ F 59

60 Threshold voltage ( for strong inversion) φ s = 2φ F At threshold we can neglect the inversion charge Q N compared with the depletion charge Q D Q = Q + Q Q S N D D Recalling that V Q Q V = φ φ C S GB FB s s Cox and solving for Q de ρ qna D ρ qna ; = with E( xd ) 0 E ( xd x) dx ε = = s ε (depletion approx.) s dφ qn qn E xd x xd x φ x = 0 = φ = 2φ 2φ = dx 2ε 2ε s = A with φ ( ) = 0 φ ( ) = ( ) 2 ( ) A 2 s F F d s Q qn x = 2 qε N φ = γc 2 φ D A d s A s ox F D ox x it follows that V = V V + 2φ + γ 2 φ T GB φ = 2φ FB F F γ = s F 2 qε N / C s A ox Body effect factor 60

61 MOSFET in subthreshold (V GS < V T ) and linear region (low V DS ) MOSFET in strong inversion (V GS >V T ) and linear region (low V DS ) 61

62 MOSFET for V GS >V T in the triode region MOSFET for V GS >V T in the saturation region 62

63 5.3 I-V Characteristics of Enhancement Mode MOSFETs V S V G 0V N + N + V D ions electrons V S V G V D 0V 2V 0V N + N + P P B B ( a ) V G = 0V V S = V D = 0V ( b ) V G = 2V V S = V D = 0V V S V G V D 1V 2V 1V N + N + V G N + N + 1V ( c ) V G = 2V V S = V D = 1V P B ( d ) V G = 2V P B V S = 0V V D = 1V 63

64 5.3 I-V Characteristics of Enhancement Mode MOSFETs φ 2φ s F at source end of channel φ 2φ + V s F DS at drain end of channel V Q + Q V = φ N D C GB FB s ox V = V + 2φ + γ 2 φ T FB F F φs 2φ F + V Q = γ C 2φ + V D ox F γ C ox 2φ F ( ) Q C V V V N ox GS T The dependence of Q D on V is accounted for in more advanced models 64

65 5.3 I-V Characteristics of Enhancement Mode MOSFETs φ 2φ s F at source end of channel φ 2φ + V s F DS at drain end of channel Strong inversion model: the electron (inversion) charge density along the channel is Q N = - C OX ( V GS V T - V ) with 0<V<V DS and the current is due to drift (Ohm s law valid in each channel element) 65

66 MOSFET current law -I Resistance of channel element of length y y dy W Inversion channel depth x I D dv L dr ch I D dy 1 dy = = W x qnµ WQ µ N 66

67 MOSFET current law -II Ohm s Law applied to the channel element of width W and length dy dy dv = drch ID drch = W µ Q I dy = W µ Q dv D Integrating the eq. above from source to drain L V N DS D 0 0 I I dy = W µ Q dv D W = L µ V DS 0 N N Q dv N 67

68 MOSFET current law -III ( ) Q = C V V V N ox GS T V GS Q C N OX V DS = V DSSAT V T + V V T 0 source VDS drain V( channel potential ) 68

69 MOSFET current law -IV Substituting the inversion charge density given by Q N = - C OX ( V GS V T - V ) in I D V DS = W L µ 0 Q dv N it follows that V DS W I = µ C V V V dv ( ) D ox GS T L 0 W 1 I = µ C ( V V ) V V L 2 2 D ox GS T DS DS 69

70 Bulk effect We have neglected the variation of the depletion charge under the channel Including this effect reduces the drain current W I = ( ) 2 D Cox VGS VT 2Ln µ Cox 1 = C + C n Typical values of n ~ 1.1 to 1.5 n is a slight function of V G ox d 70

71 The output characteristics of the MOSFET in saturation W ( ) 2 V ID = µ Cox VGS VT 1+ 2L V if V DS V DSSAT, V GS V T DS A r o = output resistance: i v D DS Q -1 = V V DS + V I D A A r o if VDS << ID V A 71

72 Channel length modulation µc W I = V -V 2 L ( ) 2 ox D GS T IDSAT L I D = IDSAT 1+ L 1- LM L M L = L M - L L V = L V M DS A k n V ID = VGS VT 1+ 2 V ( ) 2 DS A v GS v DS n + Pinchoff point L L L M Channel length modulation n + x 72

73 Summary of DC equations for the MOSFET G D S n-channel D I D B G G or V T > 0 V DS 0 S D S p-channel B G V T < 0 V DS 0 ( a ) v GS < V T Cutoff region, i D 0 v GS V T ( b ) v GS V T Triode region v GS V T 2 ( v V ) v v V ID = Cox ( VGS VT ) VDS VDS v v V ( v V ) GD T DS GS T K = µc D S I D DS GS T GD T ( b ) v GS V T Saturation region v GS V T W 2L µ OX ( vgd V T ) vds vgs VT I = ( ) 2 D Cox V GS VT v v V ( v V ) W L W 1 L µ 2 or DS GS T GD T i D ( b ) ( c ) V GS2 V GS2 ( c ) ( b ) i D V GS1 V GS1 ( a ) V DS V DS ( a ) 73

74 nmos Inverter Circuit-I V = 5 V DD 80uA 5 V V = 3.0 V GS R v O D R A I N 60uA V = 2.5 V GS v I i D + M S v DS C U R R E N T 40uA V = 2.0 V GS 20uA - V = 1.5 V GS 0A 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V NMOS inverter with resistive load V DS MOSFET output characteristics and load line V DD = 5 V R = 95 kω Load line: i D = V DD R v DS 74

75 6.0V nmos Inverter Circuit-II 5.0V V = 5 V OH -1 NMOS Inverter with Resistor Load 60 i D (µa) O u t p u t V o l t a g e 4.0V 3.0V 2.0V V -1 V = 0.25 V OL V V IL IH 0V 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V v I Simulated transfer characteristic of an NMOS logic gate with resistive load Drain current vs. input voltage V I Drawback: current consumption 50 µa if the input is high 75

76 Inverter circuit PMOS transistor load 76

77 CMOS INVERTER LOGIC THRESHOLD-I At V M both transistors are saturated Wn I = C V V 2L µ ( ) 2 Dn n ox M Tn n Wp I = C V V V 2L µ + ( ) 2 Dp p ox DD M Tp p 77

78 CMOS INVERTER LOGIC THRESHOLD-II Define k = W C L µ n n n ox n k = W C L µ p P p ox p Since I Dn = I Dp Then k n k 2 p ( V V ) = ( V V + V ) 2 M Tn DD M Tp 2 2 Solve for V M V M = k V + V + V 1+ ( ) p Tn DD Tp kn k k p n 78

79 CMOS INVERTER LOGIC THRESHOLD-III Symmetric case This implies VTp = VTn k p = kn W L p p W 2 L n n V = M V DD 2 Asymmetric cases k n >> k p V M V Tn k n V V + V << k p M DD Tp 79

80 Modeling the series association of MOSFETs W / L ( ) eq = W / L W / L ( ) ( ) S W / L + W / L D ( ) ( ) S D 80

81 Experimental Results NAND-2 DC Transfer Curve TSMC 0.35µm Technology V i =V A V B =V DD V i =V A =V B 81

82 Dynamic Operation of the CMOS Inverter - 2 v I High-to-low output transition in a CMOS inverter M P V = 5 V DD v O v = 5 V I v (0+) = 5V O i D I M Approximation as a linear resistor V R = I DSsat M v i =V DD M N C M N C V DSsat V DD v o v o 0 (a) (b) v I v O T 0 + 5V 0 V 0 t + 5V 0 V 0 t v o V DSsat exp ( t T ) RC 0 t T 0 V = C DD V I M DSsat 82

83 Subthreshold Leakage Component 83

84 Leakage Vdd Vout Drain Junction Leakage GATE N + N + P V dd Sub-Threshold Current Reverse Leakage Current Sub-Threshold Current usually Dominant Factor Reverse-Biased Diode Leakage 84

85 Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question ( ? V) Reduce switching activity Reduce physical capacitance 85

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