CHAPTER 5 MOS FIELDEFFECT TRANSISTORS


 Julianna Martin
 4 years ago
 Views:
Transcription
1 CHAPTER 5 MOS FIELDEFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancementtype NMOS transistor 5.3 IV characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5 MOS logic circuits 5.6 Some other considerations on MOSFETs 1
2 The ideal twoterminal MOS structure t ox 0 + φ S _ x Q G Q S V G N A Ptype silicon M O S V G φ = s Q C t ox  oxide thickness ε ox  permittivity of oxide G ox Charge conservation Q G + Q = φ S  surface potential S V G C ox = = φ C ox  oxide capacitance/unit area Q G (Q S )  gate (semiconductor) charge/ unit area 0 N A acceptor concentration What s the electric field E ox inside the oxide? s ε t ox ox Q C 2 S ox Potential balance equation
3 The ideal twoterminal MOS structure V G V G = φ s Q C S ox Flat band Q G M ln p, n p N A t ox 0 + φ S Q S O S metal oxide n silicon n 2 i / N A _ x t ox 0 Carrier concentration along x for φ S =Q S =0 x N A Ptype silicon p = N A Reference potential (gnd) n = n 2 i / N A 3
4 The ideal twoterminal MOS structure t ox 0 + φ S _ x Q G Q S V G N A Ptype silicon M O S ln p, n metal Carrier concentration along x for φ S >0 (Q S <0) p and n vary along x according to Boltzmann statistics p = p e = N e Reference potential (gnd) oxide t ox 0 o p n φ / φ t φ / φ t A 2 φ / φ ni φ / φ n = noe t = e N p A = N A V n = n 2 i / N A G = φ t s Q C silicon n S ox N A 2 i / 4 N x A
5 The flatband voltage (V FB ) The flatband voltage is the gatetobulk voltage required to impose φ S =0 (and Q S =0). When V GB =V FB silicon is neutral everywhere. V = V FB GB φ = Q = 0 s S Why is the flatband voltage not equal to zero? 1. Charges inside the insulator and at the semiconductorinsulator interface 2. Contact potential between the gate and the semiconductor substrate 5
6 The flatband voltage (V FB ) The effect of contact potential and oxide charges can be counterbalanced by applying a gatebulk voltage called the flatband voltage V FB. V GB = V FB Q S =0 B G psubstrate ln p, n metal The potential balance equation then becomes V oxide t ox 0 p n Q V = φ C G FB s S ox silicon n 2 i / 6 N A n i x N A
7 Regions of operation of the MOSFET: Accumulation (psubstrate) V GB G Q G Q S psubstrate B V φ Q G B s S < V < 0 > 0 F B Holes + accumulate in the ptype semiconductor surface 7
8 Accumulation (psubstrate) G Q G V GB x Q S psubstrate V φ G B s Q S < V < 0 > 0 F B B p = N e a qφ ( x) kt n = n N 2 qφ ( x) i kt e a 8
9 Regions of operation of the MOSFET: Depletion (psubstrate) V GB G Q o Q G Q S  V φ Q G B s S > < > 0 0 V F B Holes evacuate from the P semiconductor surface and acceptor ion charges become uncovered  B 9
10 Depletion (psubstrate) G Q G n = n N 2 qφ ( x) i kt a e p = N e a qφ ( x) kt V GB Q   S  p φ s > 0 B n n i 10
11 Regions of operation: Depletion (psubstrate) (depletion approx.) ρ ρ = qn ; 0< x x A =0 ; x> x d d E qn A x d εs qn A E= ( xd x); 0< x x ε s =0 ; x> x d d qn 0 A oxide silicon x d Q qn x = 2 qε N φ = γc φ D A d s A s ox s γ = 2 qε sn A / Cox x oxide dφ qn E = with φ xd = 0 x = xd x dx 2ε s qn A 2 φ ( x = 0) = φs = xd 2ε A ( ) φ ( ) ( ) 2 s 0 silicon φ φ s x d x Body effect factor oxide 0 silicon x d x 11
12 Regions of operation of the MOSFET: Inversion (psubstrate) φ s Q S > φ F < 0 Q G G Many electrons approach the surface! V GB Q o Q S metal ln p, n oxide p n silicon n 2 i / N A n i N A B t ox 0 When φ = φ p( x = 0) = n( x = 0) = n s F i x 12
13 Regions of operation of the MOSFET  Inversion (psubstrate): φs > φf Φ F is the Fermi potential p = n = N e n N a 2 i a qφ ( x) kt e qφ ( x) kt At this point p=n=n i and φ=φ F n kt N n( φ = φ ) = n = e φ = ln N q n 2 qφf i kt F i F a The semiconductor operates in inversion when φ S >φ F For φ >φ F the concentration of minority carriers (n) at the semiconductoroxide interface becomes higher than that of majority carriers (p); the semiconductor operates in the inversion region 13 i a
14 Strong inversion : the concentration of minority carriers (n) becomes higher than that of holes (majority carriers) deep in the bulk p = n = N e n N a 2 i a qφ ( x) kt e qφ ( x) kt 2 qφ ni kt N kt a n = Na = e φ = 2 ln = 2φ F N q n a i The semiconductor operates in strong inversion when φ S >2φ F 14
15 Operating regions of the MOSFET: Summary log p, n 0 n p silicon Accumulation N A n i n 2 i / N A x φ < 0; Q > 0 s S log p, n p n 0 Depletion silicon N A n i n 2 i / N A x 0 < φ < φ ; Q < 0 s F S log p, n 0 N A n i log p, n N A n i p p silicon silicon n n n 2 i / N A n 2 i / N A 0 x x Strong inversion Weak inversion φ < φ < 2 φ ; Q < 0 2 φf < φs ; QS < 0 F s F S What is n(x) and p(x) if V GB =V FB? 15
16 Threshold voltage V T ( for strong inversion) Gate voltage for which φ = 2 s φ F V = V V + 2φ + γ 2 φ φ φ T GB = 2 FB F F s F Q qn x = 2 qε N φ = γc 2 φ D A d s A s ox F γ = 2 qε N / C Body effect factor s A ox strong inversion ( ) Q = C V V N ox GB T weak inversion 16
17 Smallsignal equivalent circuit of the MOS capacitor in weak inversion C gb dqg dqs dqs 1 = = = = dv dqs d s 1 GB dv φ GB dφs + C dq C V V = φ Q / C GB FB s S ox ox S ox In weak inversion Q N /Q D <<1 V GB C s ( + Q ) dq d Q dq dφ dφ dφ S D N D = = = s s s C d C ox φ s C d : depletion capacitance C d C gb = C C ox d 17
18 Weak inversion model of the MOS device φ s dqd Cox Q γ γc φ C = ( n 1) C dφ 2 φ = D ox s d ox s s depletion region V GB ptype neutral region V GB C ox C d φ s n (slope factor), a dimensionless factor, is a function of φ s, but let us assume it is a constant. d C φ s = ox = GB ox d 1 dv C + C n 1 φ = 2φ + n ( V V ) s F GB T (I) Integrating (I) between φ s and φ s = 2φ F (V GB =V T ) leads to Boltzmann statistics applied to the electron charge density (Q N ) Q N φ s VGB V T exp exp φt nφt Note: The symbol n has been used for both electron concentration and slope factor. 18
19 5.2 The EnhancementType NMOS Transistor n + Source Region W S Channel Region B L G n n+ + Drain Region Metal D Silicon Dioxide ( SiO ) 2 PType Substrate (Body) 0.8 µ CMOS technology L min = 0.8 µm metal width 1.4 µm Wmin = 2.0 µm t ox = 160 Å X j = 0.40 µm Source (S) v S i i G i S D Gate (G) n + Channel Region n + L v G PType Substrate Body (B) v D Drain (D) x j i B ( a ) NMOS transistor structure ( b ) cross section and ( c ) circuit symbol G D i D i G i B i S B v B i G = 0 i B = 0 i D = i S S 19
20 Energy barrier at source controlled by both source and gate voltages Energy barrier at drain controlled by both drain and gate voltages /Silicon%20Valley/Pages/snug2012keynote 3dfinfet.aspx 20
21 1 I = W C V V V V 2 2 ( ) L µ D ox GS T DS DS V GS V T V DS V DSSAT For small V DS : W I C ( V V ) V L µ D ox GS T DS and did = W C ox V GS V T DS dv L µ ( ) 8.00e4 V = 5 V GS DrainSource Current (A) 6.00e e e4 V GS = 4 V V GS = 3 V V = 2 V GS 0.00e DrainSource Voltage (V) 0.8 NMOS iv characteristics in the linear region (V SB = 0) 21
22 2.20e e4 Linear Region V = 5 V GS I D 0 for V GS V T DrainSource Current (A) 1.80e e e e e e e e e e Pinchoff Locus V GS= 2 V 6 Saturation Region V GS= 4 V V = 3 V GS DrainSource Voltage (V) 8 V GS= 1 V Output characteristics for an NMOS transistor with V Tn = 1 V and (W/L)µ n C ox = 25 x 106 A / V G W 1 I = C V V V V 2 ( ) L µ 2 D ox GS T DS DS V GS V T V DS V DSSAT I = W C V V 2L µ D ( ) 2 D ox GS T I D B V GS V T V DS V DSSAT V D V S S 22
23 MOSFET IV RELATIONSHIP ,00E03 1,00E04 I D (A) SI V D = V G I D V D 1,00E ,00E06 MI V S = 0 V V G V S 1,00E07 WI 2.5 1,00E ,00E V G (V) 0,00E+00 5,00E01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00 4,50E+00 Commonsource characteristics 23
24 5.4 The PMOS Transistor Source v v < 0 S G v < 0 D i i S G Gate i D Drain p + Channel Region p + L NType Substrate Body i B v > 0 B Cross section of an enhancementmode PMOS transistor S D S B D I D I D G G 24
25 5.4 The CMOS Technology V (0 V) SS v I V (5 V) DD B p+ Ohmic contact S v o n+ n+ p+ p+ NMOS transistor D D ptype substrate nwell S PMOS transistor B n+ Ohmic contac Nwell CMOS structure for forming both NMOS & PMOS transistors in a single silicon substrate 25
26 5.6 MOS logic circuits: the ideal inverter 26
27 MOS logic circuits: the real inverter V IL V IH 27
28 The CMOS InverterI S V = 5 V DD V = 5 V DD R onp G D M P v I v O v I D v O G M N (a) S (b) R onn ( a ) CMOS inverter uses one NMOS and one PMOS transistor ( b ) Simplified model for the CMOS logic gate 28
29 The CMOS InverterII I Dn V in = 0 V in = 2.5 PMOS V in = 0.5 V in = 2 NMOS V in = 1 V in = 1.5 V in = 1.5 V in = 1 V in = 2 V in = 1.5 V in = 1 V in = 0.5 V in = 2.5 V in = 0 V out 29
30 The CMOS inverter: VTC and dc current O u t p u t V o l t a g e 4.0V 2.0V 1 M off N v = v o I 2 M saturated N M linear P + 1 V IL 3 M and M saturated N P M saturated P M linear N Drain current ( µa ) V v o = v I  1 V IH 0V 1.0V 2.0V 3.0V 4.0V 5.0V v I 4 5 M off P CMOS voltage transfer characteristic may be broken down into the five regions outlined in table v I ( V ) K n = K p = 50 µa / V 2 V TN = V TP = 1V P static = V DD i leakage +V DD i sc P shortcircuit = V DD i sc 30
31 Impact of Process Variations 2.5 V out (V) Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS V in (V) Process variations are electrically modeled through variations of parameters (V T, k p, k n, etc ) 31
32 Dynamic Operation of the CMOS Inverter 1 V = 5 V DD V = 5 V DD V = 5 V DD v I M P v O v = 5 V I v (0+) = 5V O v I M P v O M P v (0+) = 0V O M N C M N C M N C V = 0 V I C (a) (b) (a) (b) v I v O v I v O + 5V + 5V + 5V + 5V 0 V 0 t 0 V 0 t 0 V 0 t 0 V 0 t Hightolow output transition in a CMOS inverter Low to high output transition in a CMOS inverter C: load capacitance + interconnect capacitance + parasitic capacitance of the inverter 32
33 Dynamic Power Dissipation in CMOS Gates  1 V DD V I M P V I M N v o C v o T What is the energy dissipation for changing v o from 0 to V DD and back to 0? The energy dissipation in M P when v o changes from 0 to V DD is Assumptions: Step v i, constant C The energy stored in C when v o =V DD is E = CV 2 C ( p ) = ( p ) ( p ) = ( DD o ) E M v M i M dt V v dq V DD ( ) ( ) E M == C V v dv = C V 2 2 p DD o o DD 0 2 DD 33
34 Dynamic Power Dissipation in CMOS Gates  2 V DD V I M P V I M N v o C v o T The energy dissipation in M N when v o changes from V DD to 0 equals the energy stored in the capacitor before discharging it P CV E M v M i M dt v Cdv E C V = T 0 2 DD N = N N = o o = = C 2 V ( ) ( ) ( ) 2 DD P = f 2 C V DD DD When the operation of charging and discharging the capacitor is repeated each T seconds (or f times per second), the power dissipation is In general, the average dynamic power dissipation is 2 P = af C V DD a is the switching activity factor 34
35 CMOS Gates ( Static Logic ) V = 5 V DD V DD 10 1 PMOS Switching Network Logic Inputs Y 10 1 Y NMOS Switching Network A 2 1 B 2 1 C Basic CMOS logic gate structure Twoinput CMOS NOR gate 35
36 36
37 The complete IV relationship of the MOSFET ( strong and weak inversion) ,00E03 1,00E04 I D (A) V D = V G VD 1,00E ,00E06 V S = 0 V V G V S I D 1,00E ,00E ,00E V G (V) 0,00E+00 5,00E01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00 4,50E+00 Commonsource characteristics 37
38 Prof. James Meindl: Theoretically, the minimum supply voltage for a CMOS inverter is 2 (ln2) (kt/q) = 36 mv at room temperature (IEEE JSSC, 2000) 38
39 39
40 40
41 41
42 42
43 43
44 44
45 45
46 46
47 Seriesparallel association of MOSFETs 47
48 Regenerative Property out out v 3 f (v) v 3 fin v(v) v 1 v 1 fin v(v) v 3 f (v) v 2 v 0 Regenerative in v 0 v 2 NonRegenerative in 48
49 Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6 A chain of inverters 5 V (Volt) 3 v 0 1 v 1 v 2 Simulated response t (nsec)
50 Ring Oscillator v 0 v 1 v 2 v 3 v 4 v 5 v 0 v 1 v 5 T = 2 t p N 50
51 REFERENCES R. F. Pierret, Field Effect devices, 2 nd ed., AddisonWesley, Y. Tsividis, Mixed AnalogDigital VLSI Devices and Tecnology, World Scientific,1996. C. GalupMontoro and M. C. Schneider, MOSFET Modeling for Circuit Analysis and Design, World Scientific, M. C. Schneider and C. GalupMontoro, CMOS Analog Design Using All Region MOSFET Modeling, Cambridge, R. Howe, and C. Sodini. Microelectronics: An Integrated Approach. Prentice Hall, J. Rabaey, A. P. Chandrakasan, B. Nikolić, Digital Integrated Circuits: A Design Perspective, Pearson Education, L. A. Pasini Melek, Operação de Circuitos Lógicos CMOS de (ultra)baixo consumo, Dissertação de mestrado, UFSC,
52 Example: oxide capacitance (a) Calculate the oxide capacitance per unit area for t ox = 5 and 20 nm. The permittivity of silicon oxide is ε ox = 3.9ε 0. ε 0 = F/cm is the permittivity of free space. (b) Determine the area of a 1pF metaloxidemetal capacitor for the two oxide thicknesses given in (a). (c) Determine the gate charge/unit area in C/cm 2 and the number of elementary charges/µm 2 of the 1 pf capacitor for V G φ S =1 V Answer: (a) C ox = 690 nf/cm 2 = 6.9 ff/µm 2 for t ox =5 nm and C ox = 172 nf/cm 2 = 1.7 ff/µm 2 for t ox = 20 nm. (b)the capacitor areas are 145 and 580 µm 2 for oxide thicknesses of 5 and 20 nm, respectively. (c) and /µm 2 for capacitor area of 145 µm 2 and and /µm 2 for capacitor area of 580 µm 2. 52
53 Example: charge density z y W t x L Assume that the electron concentration is n = cm 3, L=W=1 um, t=0.1 um (a) Calculate the volumetric charge density (b) Calculate the total number of electrons and the corresponding charge inside the volume (c) Calculate the (areal) charge density seen from the zdirection Answer: (a) ρ= C/cm 3 (b) Number of electrons = 10 3, charge = 1.6 x C (c) charge density Q n = 1.6 x 108 C/cm 2. 53
54 The flatband voltage (V FB ) 1. Charges inside the insulator and at the semiconductorinsulator interface induce a semiconductor charge at zero bias. ρ(x) Q o Q G +Q S +Q o =0 Metal Oxide Silicon Q S QG x V GB =0 V FB G Q o Q G Q   S B ρ(x) Q o Q G +Q S +Q o =0 Metal Oxide Silicon Q G t ox Q S =0 0 x V GB =V FB G   Q G Qo Q S =0 54 B
55 The flatband voltage (V FB ) 2. In equilibrium (with the two terminals shortened), the contact potential between the gate and the semiconductor substrate of the MOS induces charges in the gate and the semiconductor for V GB =0. ρ(x) Q G +Q S =0 Metal Oxide Silicon Q G x V GB =0 ρ(x) Q G =Q S =0 Metal Oxide Silicon x V GB =V FB t ox 0 55
56 Example: flatband voltage V V (a) Determine the expression for the flatband voltage of n + polysilicongate on ptype silicon (b) Calculate the flatband voltage for an n + polysilicongate on ptype silicon structure with N A = atoms/cm 3. Answer: (a) In equilibrium, by analogy with an n + p junction, the potential of the n + region is positive with respect to that of the p region. The flatband condition is obtained by applying a negative potential to the n + gate with respect to the ptype semiconductor of value (b) N A _ + = φ _ + = 0.56 V φ ln ni FB n p bi n p t FB 7 ( ) = 0.56 V φ ln 10 = 980 mv t G n + gate psubstrate B G n + gate 980 mv psubstrate B 56
57 Example: threshold voltage Estimate V T for an nchannel transistor with n + polysilicon gate, N A =10 17 atoms/cm 3 and t ox =5 nm. Answer: The flatband voltage (slide 12) is V; φ F =0.419; C ox = 690 nf/cm 2. The bodyeffect factor is γ = 2 qε N / C = V s A ox V V + 2φ + γ 2 φ = = 0.1V T FB F F For this low value of the threshold voltage, the offcurrent (for V GS =0) is too high for digital circuits (see subthreshold leakage). Solution to control the magnitude of the threshold voltage a nonuniform highlow channel doping N S N A 57
58 Exact relationship between surface potential and applied gate voltage V G for the MOS capacitor Approximation Strong inversion ( ) Q = C V V N ox GB T Depletion/weak inversion Accumulation Q N VGB V T exp nφt 58
59 Threshold voltage V T ( for strong inversion) Gate voltage for which φ = 2 QS = QN + QD s φ F Q N Q D Electron (carrier) charge Depletion (ion) charge Charge sheet approx. Depletion approx. 2φ F 59
60 Threshold voltage ( for strong inversion) φ s = 2φ F At threshold we can neglect the inversion charge Q N compared with the depletion charge Q D Q = Q + Q Q S N D D Recalling that V Q Q V = φ φ C S GB FB s s Cox and solving for Q de ρ qna D ρ qna ; = with E( xd ) 0 E ( xd x) dx ε = = s ε (depletion approx.) s dφ qn qn E xd x xd x φ x = 0 = φ = 2φ 2φ = dx 2ε 2ε s = A with φ ( ) = 0 φ ( ) = ( ) 2 ( ) A 2 s F F d s Q qn x = 2 qε N φ = γc 2 φ D A d s A s ox F D ox x it follows that V = V V + 2φ + γ 2 φ T GB φ = 2φ FB F F γ = s F 2 qε N / C s A ox Body effect factor 60
61 MOSFET in subthreshold (V GS < V T ) and linear region (low V DS ) MOSFET in strong inversion (V GS >V T ) and linear region (low V DS ) 61
62 MOSFET for V GS >V T in the triode region MOSFET for V GS >V T in the saturation region 62
63 5.3 IV Characteristics of Enhancement Mode MOSFETs V S V G 0V N + N + V D ions electrons V S V G V D 0V 2V 0V N + N + P P B B ( a ) V G = 0V V S = V D = 0V ( b ) V G = 2V V S = V D = 0V V S V G V D 1V 2V 1V N + N + V G N + N + 1V ( c ) V G = 2V V S = V D = 1V P B ( d ) V G = 2V P B V S = 0V V D = 1V 63
64 5.3 IV Characteristics of Enhancement Mode MOSFETs φ 2φ s F at source end of channel φ 2φ + V s F DS at drain end of channel V Q + Q V = φ N D C GB FB s ox V = V + 2φ + γ 2 φ T FB F F φs 2φ F + V Q = γ C 2φ + V D ox F γ C ox 2φ F ( ) Q C V V V N ox GS T The dependence of Q D on V is accounted for in more advanced models 64
65 5.3 IV Characteristics of Enhancement Mode MOSFETs φ 2φ s F at source end of channel φ 2φ + V s F DS at drain end of channel Strong inversion model: the electron (inversion) charge density along the channel is Q N =  C OX ( V GS V T  V ) with 0<V<V DS and the current is due to drift (Ohm s law valid in each channel element) 65
66 MOSFET current law I Resistance of channel element of length y y dy W Inversion channel depth x I D dv L dr ch I D dy 1 dy = = W x qnµ WQ µ N 66
67 MOSFET current law II Ohm s Law applied to the channel element of width W and length dy dy dv = drch ID drch = W µ Q I dy = W µ Q dv D Integrating the eq. above from source to drain L V N DS D 0 0 I I dy = W µ Q dv D W = L µ V DS 0 N N Q dv N 67
68 MOSFET current law III ( ) Q = C V V V N ox GS T V GS Q C N OX V DS = V DSSAT V T + V V T 0 source VDS drain V( channel potential ) 68
69 MOSFET current law IV Substituting the inversion charge density given by Q N =  C OX ( V GS V T  V ) in I D V DS = W L µ 0 Q dv N it follows that V DS W I = µ C V V V dv ( ) D ox GS T L 0 W 1 I = µ C ( V V ) V V L 2 2 D ox GS T DS DS 69
70 Bulk effect We have neglected the variation of the depletion charge under the channel Including this effect reduces the drain current W I = ( ) 2 D Cox VGS VT 2Ln µ Cox 1 = C + C n Typical values of n ~ 1.1 to 1.5 n is a slight function of V G ox d 70
71 The output characteristics of the MOSFET in saturation W ( ) 2 V ID = µ Cox VGS VT 1+ 2L V if V DS V DSSAT, V GS V T DS A r o = output resistance: i v D DS Q 1 = V V DS + V I D A A r o if VDS << ID V A 71
72 Channel length modulation µc W I = V V 2 L ( ) 2 ox D GS T IDSAT L I D = IDSAT 1+ L 1 LM L M L = L M  L L V = L V M DS A k n V ID = VGS VT 1+ 2 V ( ) 2 DS A v GS v DS n + Pinchoff point L L L M Channel length modulation n + x 72
73 Summary of DC equations for the MOSFET G D S nchannel D I D B G G or V T > 0 V DS 0 S D S pchannel B G V T < 0 V DS 0 ( a ) v GS < V T Cutoff region, i D 0 v GS V T ( b ) v GS V T Triode region v GS V T 2 ( v V ) v v V ID = Cox ( VGS VT ) VDS VDS v v V ( v V ) GD T DS GS T K = µc D S I D DS GS T GD T ( b ) v GS V T Saturation region v GS V T W 2L µ OX ( vgd V T ) vds vgs VT I = ( ) 2 D Cox V GS VT v v V ( v V ) W L W 1 L µ 2 or DS GS T GD T i D ( b ) ( c ) V GS2 V GS2 ( c ) ( b ) i D V GS1 V GS1 ( a ) V DS V DS ( a ) 73
74 nmos Inverter CircuitI V = 5 V DD 80uA 5 V V = 3.0 V GS R v O D R A I N 60uA V = 2.5 V GS v I i D + M S v DS C U R R E N T 40uA V = 2.0 V GS 20uA  V = 1.5 V GS 0A 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V NMOS inverter with resistive load V DS MOSFET output characteristics and load line V DD = 5 V R = 95 kω Load line: i D = V DD R v DS 74
75 6.0V nmos Inverter CircuitII 5.0V V = 5 V OH 1 NMOS Inverter with Resistor Load 60 i D (µa) O u t p u t V o l t a g e 4.0V 3.0V 2.0V V 1 V = 0.25 V OL V V IL IH 0V 0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V v I Simulated transfer characteristic of an NMOS logic gate with resistive load Drain current vs. input voltage V I Drawback: current consumption 50 µa if the input is high 75
76 Inverter circuit PMOS transistor load 76
77 CMOS INVERTER LOGIC THRESHOLDI At V M both transistors are saturated Wn I = C V V 2L µ ( ) 2 Dn n ox M Tn n Wp I = C V V V 2L µ + ( ) 2 Dp p ox DD M Tp p 77
78 CMOS INVERTER LOGIC THRESHOLDII Define k = W C L µ n n n ox n k = W C L µ p P p ox p Since I Dn = I Dp Then k n k 2 p ( V V ) = ( V V + V ) 2 M Tn DD M Tp 2 2 Solve for V M V M = k V + V + V 1+ ( ) p Tn DD Tp kn k k p n 78
79 CMOS INVERTER LOGIC THRESHOLDIII Symmetric case This implies VTp = VTn k p = kn W L p p W 2 L n n V = M V DD 2 Asymmetric cases k n >> k p V M V Tn k n V V + V << k p M DD Tp 79
80 Modeling the series association of MOSFETs W / L ( ) eq = W / L W / L ( ) ( ) S W / L + W / L D ( ) ( ) S D 80
81 Experimental Results NAND2 DC Transfer Curve TSMC 0.35µm Technology V i =V A V B =V DD V i =V A =V B 81
82 Dynamic Operation of the CMOS Inverter  2 v I Hightolow output transition in a CMOS inverter M P V = 5 V DD v O v = 5 V I v (0+) = 5V O i D I M Approximation as a linear resistor V R = I DSsat M v i =V DD M N C M N C V DSsat V DD v o v o 0 (a) (b) v I v O T 0 + 5V 0 V 0 t + 5V 0 V 0 t v o V DSsat exp ( t T ) RC 0 t T 0 V = C DD V I M DSsat 82
83 Subthreshold Leakage Component 83
84 Leakage Vdd Vout Drain Junction Leakage GATE N + N + P V dd SubThreshold Current Reverse Leakage Current SubThreshold Current usually Dominant Factor ReverseBiased Diode Leakage 84
85 Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question ( ? V) Reduce switching activity Reduce physical capacitance 85
86 /Silicon%20Valley/Pages/snug2012keynote 3dfinfet.aspx 86
87 /Silicon%20Valley/Pages/snug2012keynote 3dfinfet.aspx 87
FIELDEFFECT TRANSISTORS
FIELEFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancementtype NMOS transistor 3 IV characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Crosssection and layout
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationFundamentals of the Metal Oxide Semiconductor FieldEffect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor FieldEffect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE ptype doped Si (N A = 10 15 to 10 16 cm 3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationChapter 2 CMOS Transistor Theory. JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor JinFu Li, EE,
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ualwell TrenchIsolated
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationEE105  Fall 2005 Microelectronic Devices and Circuits
EE105  Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cutoff. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cutoff. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
More informationChapter 2 MOS Transistor theory
Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majoritycarrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 1  The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15
ESE 570 MOS TRANSISTOR THEORY Part 1 TwoTerminal MOS Structure 2 GATE Si Oxide interface n n Mass Action Law VB 2 Chemical Periodic Table Donors American Chemical Society (ACS) Acceptors Metalloids 3 Ideal
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationReview of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model
Content MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 20092013 Digital Switching 1 Content MOS
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationElectrical Characteristics of MOS Devices
Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Thresholdvoltage
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationMOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.
INEL 6055  Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ
More informationECE 497 JS Lecture  12 Device Technologies
ECE 497 JS Lecture  12 Device Technologies Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationP. R. Nelson 1 ECE418  VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418  VLSI Midterm Exam Solutions 1. (8 points) Draw the crosssection view for AA. The crosssection view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! medamine.miled@polymtl.ca!
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and MK Lee 1. The purest semiconductor crystals it is possible
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET NType, PType. Semiconductor Physics.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 217 MOS Transistor Theory, MOS Model Lecture Outline! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff
More informationECE305: Fall 2017 MOS Capacitors and Transistors
ECE305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525530, 563599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationLecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)
Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture
More informationLecture 29  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 20, 2007
6.720J/3.43J  Integrated Microelectronic Devices  Spring 2007 Lecture 291 Lecture 29  The Long MetalOxideSemiconductor FieldEffect Transistor (cont.) April 20, 2007 Contents: 1. Nonideal and secondorder
More informationContent. MIS Capacitor. Accumulation Depletion Inversion MOS CAPACITOR. A Cantoni Digital Switching
Content MIS Capacitor Accumulation Depletion Inversion MOS CAPACITOR 1 MIS Capacitor Metal Oxide C ox psi C s Components of a capacitance model for the MIS structure 2 MIS Capacitor Accumulation ρ( x)
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationLecture 6 PN Junction and MOS Electrostatics(III) MetalOxideSemiconductor Structure
Lecture 6 PN Junction and MOS Electrostatics(III) MetalOxideSemiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with
More informationQuantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.
Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to
More informationECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University
NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the
More informationCMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors
CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier
More informationThe Intrinsic Silicon
The Intrinsic ilicon Thermally generated electrons and holes Carrier concentration p i =n i ni=1.45x10 10 cm3 @ room temp Generally: n i = 3.1X10 16 T 3/2 e 1.21/2KT cm 3 T= temperature in K o (egrees
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationCharge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn )
The Inverted MO Capacitor (V > V Tn ) We consider the surface potential as Þxed (ÒpinnedÓ) at φ s,max =  φ p φ(x).5 V. V V ox Charge torage in the MO tructure Three regions of operation: Accumulation:
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and crosssectional area 100µm 2
More informationMOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor
MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste
More informationEE 330 Lecture 16. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationLong Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to MetalOxideSemiconductor FieldEffect transistors (MOSFET) by considering the following structure:
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationII III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing
II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III  V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band
More informationLecture 7  PN Junction and MOS Electrostatics (IV) Electrostatics of MetalOxideSemiconductor Structure. September 29, 2005
6.12  Microelectronic Devices and Circuits  Fall 25 Lecture 71 Lecture 7  PN Junction and MOS Electrostatics (IV) Electrostatics of MetalOideSemiconductor Structure September 29, 25 Contents: 1.
More informationUniversity of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm 3 @
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ FieldOxyde (SiO 2 ) psubstrate p+ stopper Bulk Contact CROSSSECTION of NMOS Transistor CrossSection of CMOS Technology MOS transistors
More information