The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices
|
|
|
- Rafe McDowell
- 5 years ago
- Views:
Transcription
1 The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices Zhiping Yu and Jinyu Zhang Institute of Microelectronics Tsinghua University, Beijing, China
2 Outline The major concerns near the end of MOS scaling What is quantum capacitance (QC) and why has it mostly been ignored in FET compact modeling? Modeling and equivalent circuits for QC Carbon-NanoTube FET (CNT-FET), a classical Example for illustrating QC Compact model for Graphene FET (GFET) and its application in design of a distributed amplifier Conclusions June 27, 2016 MOS-AK Shanghai, June 26-28,
3 Driving Force for Further MOS Scaling It s low power, low voltage, and low gate delay (powerdelay product) From planar to FinFET, and from tunneling FET to novel nano-electronic devices (new channel materials) V ds = V dd 22nm planar V = 0 ds Vdd=0.68V Source: Bohr/Mistry slides, May
4 Important Means to Further MOS Scaling New device structures Gate-All-Around Nanowire (GAA-NW) FETs Tunneling FETs (tfets) Junctionless (JL) FETs New channel materials III-V CMOS, e.g., InAs for nmos and GaSb for pmos on GaAs substrate 2D materials, typical graphene, and emerging MoS 2, WSe 2, black phosphorous (BP), etc. 1D materials, mainly carbon nanotube (CNT) June 27, 2016 MOS-AK Shanghai, June 26-28,
5 Critical Device/Material Parameters to Look At Devices Subthreshold swing (SS): break through the 60mV/dec limit I on and I on /I off ratio Off-state leakage (drain controllability over gate) Channel materials Mobility Density of States (DOS) June 27, 2016 MOS-AK Shanghai, June 26-28,
6 Tunneling FETs and Small SS K. Jeon, SEMATECH/UCB, VLSI 10 source side pmos Features: I on /I off : 10 8 n-i-p on 40nm BOX NiSi source structure High field pocket Recessed source-side silicon SS<60 mv/dec for 3-decades of I D June 27, 2016 MOS-AK Shanghai, June 26-28,
7 CNT-FET and Small Gate Delay J. Appenzeller, IBM, PRL 04 pmos, Vds=-0.5V ambipolar Tunneling thru SB band-to-band tunneling June 27, 2016 MOS-AK Shanghai, June 26-28,
8 Why Need to Model Quantum Capacitance (QC) An accurate total (and especially the intrinsic) gate capacitance is important in evaluating the transistor performance (gate delay, say) C V I delay gate dd D Channel materials are assessed for both mobility and density-of-states (DOS), often there is a trade-off (high m implies low DOS) Nano-electronic (and gate-all-around) devices don t have body contact to their channel. June 27, 2016 MOS-AK Shanghai, June 26-28,
9 QC Is Not New: MOS Capacitor Has DOS Capacitance Having bulk contact to channel q s V GB Q inv q n x dx, C inv / V F t n n e N e n i N N e i C V E g C 2k T B Q inv E E / k T F C B S June 27, 2016 MOS-AK Shanghai, June 26-28,
10 Then, Why Quantum (Capacitance)? First coined by S. Luryi of Bell Labs, APL 88 for 2DEG 2DEG C Qi 1e 2 * 2 qm Ei EF kbt 2D DOS e.g., m*=0.98m 0 for Si m l D. Jin, MS thesis, MIT, 2010 June 27, 2016 MOS-AK Shanghai, June 26-28,
11 Impact of Quantum Capacitance B. Yu, UCSD, T-ED, 08 June 27,
12 Effective Mass of DOS for Different Semiconductors G. Jin, MIT, MS Thesis, 10 Si: 1.08 m 0 GaAs: m 0 InAs: m 0 In 0.53 Ga 0.47 As: 0.04 m 0 June 27,
13 DOS Dependence on Electronic Energy for 1/2/3D D D D ck k /2 V 2 m* N E E E 2 3D c in dispersion relation of E E c k k E E E c c E E and p is the power of k, e.g., p 2 for parabolic k E E 0 k p 1D 2D 3D J. Mintmire PRL 98 D. Jin MIT MS Thesis 10 Wiki June 27,
14 DOS for Nanowire B. Yu, UCSD, T-ED 08 Si nanowire of r = 2.5nm June 27, 2016 MOS-AK Shanghai, June 26-28,
15 Quantum Capacitance (QC): Modeling Approach Ballistic transport assumption: provide knowledge of Fermi level in channel nmos Electron Energy channel carrier density -q U SCF q S S ch D A. Raychowdhury, T-ICCAD 04 A. Rahman, T-ED 04 June 27, 2016 MOS-AK Shanghai, June 26-28,
16 Definition of QC: C q June 27, 2016 MOS-AK Shanghai, June 26-28,
17 QC (cont d): Equivalent Circuit Use charge balance principle to find V ch : C V V Q V V Q V V S G ox G ch S ch S D ch D V G large signal model C ox V ch D Incremental (small signal) capacitance network V S ch G qs qd C June 27, 2016 ox CqS CqD Vch V C qs C qd ch 17 Q S ox S V V, C, C channel mobile charge Q D C Q Q new circuit symbol V D q for quantum D C ox
18 Application of QC to tfet Z. Yu, Tsinghua, ICSICT 12 Compared to CH S. Fregonese, TED 09 June 27,
19 Quantum Capacitance in III-V FETs D. Jin, MS thesis, MIT, q Q i q Q i q Q i EF EC EF Ei Ei EC CQi Ccent, i June 27, 2016 MOS-AK Shanghai, June 26-28,
20 Thermal Emission vs. Band-to-Band Tunneling (BtBT): Band-Pass Filtering Now, consider using BtBT to improve SS J. Knoch, IBM, DRC 05 T E 3/2 4 2 m* E g const exp 3q E, g cnt ox t t ox cnt June 27, 2016 MOS-AK Shanghai, June 26-28,
21 SCE: Short-Channel Effect J. Knoch, IBM Zurich Lab, Phys. Stat. Sol. 08 Look for gate control drain control (DIBL) 0 f long channel or SCE: L vs. is influenced by d June 27, 2016 MOS-AK Shanghai, June 26-28,
22 SS of CNT-FET as a Function of t ox : a Measure of Gate Controllability J. Appenzeller, IBM, PRL 02 pmos large small DIBL J. Knoch, IBM Zurich, PSS nm SiO 2 20nm HfO 2 June 27, 2016 MOS-AK Shanghai, June 26-28,
23 Charge Pile-up in Channel of CNT-FET through BtBT J. Appenzeller, IBM, PRL 04 (both experiment and simulation by NEGF) S. Fregonese, U Bordeaux, T-ED, 09 Double gates J. Knoch, IBM, PSS 08 pmos June 27, 2016 MOS-AK Shanghai, June 26-28,
24 Dual Forces in Controlling Channel Potential: from Gate and Drain Terminals J. Knoch, IBM, PSS 08 C q 2 8 m* h E 0 f d f C C C 0 ox q d f g d Cox Cq Cd Cox Cq Cd C ox C q g 0 f For an electrostatically well-designed device at off-state C C C ox q, QCL: quantum capacitance limited d C ox C q June 27, 2016 MOS-AK Shanghai, June 26-28,
25 Advantage of 1D Transport for CNT-FET J. Knoch, IBM, PSS 08 C BtBT q, BtBT 0 f 4 2 * 3 Q E g 32 m Eg T WKB de D E f E E WKB 0 f S 1 f qt de D E f E E C T and I T q, BtBT WKB D WKB resulting in delay independent upon S 1 f T WKB June 27, 2016 MOS-AK Shanghai, June 26-28,
26 Dilemma of QCL Regime Gate control is good (channel potential closely follow the gate bias), meaning small SS Yet, the total gate capacitance becomes small, which implies small on current There may be some optimization scheme for minimizing the gate delay Similar situation for JL-FETs June 27, 2016 MOS-AK Shanghai, June 26-28,
27 Compact Model for GFET W. Zhu, Tsinghua, SISPAD 12 Features: Back gate effect on the shift Dirac voltage Reducing S/D resistance by using back gate D. Jimenez, TED 11 June 27, 2016 MOS-AK Shanghai, June 26-28,
28 More on GET Model S. Thiele, U. Ilmenau, JAP 10 C q dq dv sh ch 2 2q qv v ch 2 F Not a constant! June 27, 2016 MOS-AK Shanghai, June 26-28,
29 Central Ideal in GFET Modeling To each position x in the channel belongs a certain local potential V(x) I qn xvxw qn V xv V xw D sheet The voltage across the quantum capacitance, C q, is named as V ch. Density of States (DOS) for graphene D E 2 E E v CV 2 June 27, 2016 MOS-AK Shanghai, June 26-28, sheet Taking E 0, E qv CV F F 8, vf 10 cm/s ch
30 Self-Consistent Solution of V ch and C q J. Thielte June 27, 2016 MOS-AK Shanghai, June 26-28,
31 Four-Stage GFET Distributed Amplifier H Lyu, Tsinghua, Scientific Report 15 June 27, 2016 MOS-AK Shanghai, June 26-28,
32 Conclusions Besides carrier transport, electrostatics (including quantum effects such as quantum confinement) still plays the most central role in device modeling. It is not certain towards the end of the MOS scaling, new (channel) materials and new device structures will emerge as the mainstream IC technology The case study of quantum capacitance prepares the modeling society for the new challenges. June 27, 2016 MOS-AK Shanghai, June 26-28,
ECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
MOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
Scaling Issues in Planar FET: Dual Gate FET and FinFETs
Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar
III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis
III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis Microsystems Technology Laboratories, MIT 1 presently with Teledyne Scientific 23rd International
A Multi-Gate CMOS Compact Model BSIMMG
A Multi-Gate CMOS Compact Model BSIMMG Darsen Lu, Sriramkumar Venugopalan, Tanvir Morshed, Yogesh Singh Chauhan, Chung-Hsun Lin, Mohan Dunga, Ali Niknejad and Chenming Hu University of California, Berkeley
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
Simple Theory of the Ballistic Nanotransistor
Simple Theory of the Ballistic Nanotransistor Mark Lundstrom Purdue University Network for Computational Nanoechnology outline I) Traditional MOS theory II) A bottom-up approach III) The ballistic nanotransistor
CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS
98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC
ECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,
Integrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
Lecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
The Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University
NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the
! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
Microsystems Technology Laboratories, MIT. Teledyne Scientific Company (TSC)
Extraction of Virtual-Source Injection Velocity in sub-100 nm III-V HFETs 1,2) D.-H. Kim, 1) J. A. del Alamo, 1) D. A. Antoniadis and 2) B. Brar 1) Microsystems Technology Laboratories, MIT 2) Teledyne
EECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold
FIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
Lecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
Lecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
VLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V
Modeling and Computation of Gate Tunneling Current through Ultra Thin Gate Oxides in Double Gate MOSFETs with Ultra Thin Body Silicon Channel
Modeling and Computation of Gate Tunneling Current through Ultra Thin Gate Oxides in Double Gate MOSFETs with Ultra Thin Body Silicon Channel Bhadrinarayana L V 17 th July 2008 Microelectronics Lab, Indian
A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room).
A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room). The Final Exam will take place from 12:30PM to 3:30PM on Saturday May 12 in 60 Evans.» All of
Capacitance-Voltage characteristics of nanowire trigate MOSFET considering wave functionpenetration
Global Journal of researches in engineering Electrical and electronics engineering Volume 12 Issue 2 Version 1.0 February 2012 Type: Double Blind Peer Reviewed International Research Journal Publisher:
Lecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
ECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
Supporting information
Supporting information Design, Modeling and Fabrication of CVD Grown MoS 2 Circuits with E-Mode FETs for Large-Area Electronics Lili Yu 1*, Dina El-Damak 1*, Ujwal Radhakrishna 1, Xi Ling 1, Ahmad Zubair
High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs
High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs Prof. (Dr.) Tejas Krishnamohan Department of Electrical Engineering Stanford University, CA & Intel Corporation
Semiconductor Physics fall 2012 problems
Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each
MOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
Technology Development for InGaAs/InP-channel MOSFETs
MRS Spring Symposium, Tutorial: Advanced CMOS Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco Technology Development for InGaAs/InP-channel MOSFETs Mark Rodwell University
Introduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
ECE 305: Fall MOSFET Energy Bands
ECE 305: Fall 2016 MOSFET Energy Bands Professor Peter Bermel Electrical and Computer Engineering Purdue University, West Lafayette, IN USA pbermel@purdue.edu Pierret, Semiconductor Device Fundamentals
ECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
Evaluation of Electronic Characteristics of Double Gate Graphene Nanoribbon Field Effect Transistor for Wide Range of Temperatures
Evaluation of Electronic Characteristics of Double Gate Graphene Nanoribbon Field Effect Transistor for Wide Range of Temperatures 1 Milad Abtin, 2 Ali Naderi 1 Department of electrical engineering, Masjed
Microelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
Lecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
Lecture 6: 2D FET Electrostatics
Lecture 6: 2D FET Electrostatics 2016-02-01 Lecture 6, High Speed Devices 2014 1 Lecture 6: III-V FET DC I - MESFETs Reading Guide: Liu: 323-337 (he mainly focuses on the single heterostructure FET) Jena:
The Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
Carbon Nanotube Electronics
Carbon Nanotube Electronics Jeorg Appenzeller, Phaedon Avouris, Vincent Derycke, Stefan Heinz, Richard Martel, Marko Radosavljevic, Jerry Tersoff, Shalom Wind H.-S. Philip Wong hspwong@us.ibm.com IBM T.J.
Physics an performance of III-V nanowire heterojunction TFETs including phonon and impurity band tails:
Physics an performance of III-V nanowire heterojunction TFETs including phonon and impurity band tails: An atomistic mode space NEGF quantum transport study. A. Afzalian TSMC, Leuven, Belgium (Invited)
EE410 vs. Advanced CMOS Structures
EE410 vs. Advanced CMOS Structures Prof. Krishna S Department of Electrical Engineering S 1 EE410 CMOS Structure P + poly-si N + poly-si Al/Si alloy LPCVD PSG P + P + N + N + PMOS N-substrate NMOS P-well
EE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
Lecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
Diameter Optimization for Highest Degree of Ballisticity of Carbon Nanotube Field Effect Transistors I. Khan, O. Morshed and S. M.
Diameter Optimization for Highest Degree of Ballisticity of Carbon Nanotube Field Effect Transistors I. Khan, O. Morshed and S. M. Mominuzzaman Department of Electrical and Electronic Engineering, Bangladesh
I-V characteristics model for Carbon Nanotube Field Effect Transistors
International Journal of Engineering & Technology IJET-IJENS Vol:14 No:04 33 I-V characteristics model for Carbon Nanotube Field Effect Transistors Rebiha Marki, Chérifa Azizi and Mourad Zaabat. Abstract--
Semiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
Drift-diffusion model for single layer transition metal dichalcogenide field-effect transistors
Drift-diffusion model for single layer transition metal dichalcogenide field-effect transistors David Jiménez Departament d'enginyeria Electrònica, Escola d'enginyeria, Universitat Autònoma de Barcelona,
Device Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
EE5311- Digital IC Design
EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
Device Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
Lecture 11: MOSFET Modeling
Digital Integrated Circuits (83-313) Lecture 11: MOSFET ing Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,
Electrical Characteristics of MOS Devices
Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage
MOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
Chapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
MOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order
A Numerical Study of Scaling Issues for Schottky Barrier Carbon Nanotube Transistors
A Numerical Study of Scaling Issues for Schottky Barrier Carbon Nanotube Transistors Jing Guo, Supriyo Datta and Mark Lundstrom School of Electrical and Computer Engineering, Purdue University, West Lafayette,
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "
Lecture #27. The Short Channel Effect (SCE)
Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )
AS MOSFETS reach nanometer dimensions, power consumption
1 Analytical Model for a Tunnel Field-Effect Transistor Abstract The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. Due to the
Analysis of Band-to-band. Tunneling Structures. Title of Talk. Dimitri Antoniadis and Judy Hoyt (PIs) Jamie Teherani and Tao Yu (Students) 8/21/2012
1 Analysis of Band-to-band Title of Talk Tunneling Structures Dimitri Antoniadis and Judy Hoyt (PIs) Jamie Teherani and Tao Yu (Students) 8/21/2012 A Science & Technology Center Vertical Type-II TFET Structure
Section 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD
Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor
JFETs AND MESFETs Introduction Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor Why would an FET made of a planar capacitor with two metal plates, as
Metallic: 2n 1. +n 2. =3q Armchair structure always metallic = 2
Properties of CNT d = 2.46 n 2 2 1 + n1n2 + n2 2π Metallic: 2n 1 +n 2 =3q Armchair structure always metallic a) Graphite Valence(π) and Conduction(π*) states touch at six points(fermi points) Carbon Nanotube:
Components Research, TMG Intel Corporation *QinetiQ. Contact:
1 High-Performance 4nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (V CC =.5V) Logic Applications M. Radosavljevic,, T. Ashley*, A. Andreev*, S.
Practice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
Electrostatics of Nanowire Transistors
Electrostatics of Nanowire Transistors Jing Guo, Jing Wang, Eric Polizzi, Supriyo Datta and Mark Lundstrom School of Electrical and Computer Engineering Purdue University, West Lafayette, IN, 47907 ABSTRACTS
SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
Quantum-size effects in sub-10 nm fin width InGaAs finfets
Quantum-size effects in sub-10 nm fin width InGaAs finfets Alon Vardi, Xin Zhao, and Jesús A. del Alamo Microsystems Technology Laboratories, MIT December 9, 2015 Sponsors: DTRA NSF (E3S STC) Northrop
Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs
Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs Cheng-Ying Huang 1, Sanghoon Lee 1, Evan Wilson 3, Pengyu Long 3, Michael Povolotskyi 3, Varistha Chobpattana
ECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
Electrostatic Single-walled Carbon Nanotube (CNT) Field Effect Transistor Device Modeling
Electrostatic Single-walled Carbon Nanotube (CNT) Field Effect Transistor Device Modeling Henok Abebe The Service USC Viterbi School of Engineering Information Sciences Institute Collaborator Ellis Cumberbatch
The Future of CMOS. David Pulfrey. CHRONOLOGY of the FET. Lecture Lilienfeld s patent (BG FET) 1965 Commercialization (Fairchild)
The Future of CMOS David Pulfrey 1 CHRONOLOGY of the FET 1933 Lilienfeld s patent (BG FET) 1965 Commercialization (Fairchild) 1991 The most abundant object made by mankind (C.T. Sah) 2003 The 10 nm FET
ECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
SUPPLEMENTARY INFORMATION
SUPPLEMENTARY INFORMATION doi:10.1038/nature15387 S1. ADVANTAGES OF D MATERIALS for ULTRA SHORT-CHANNEL FIELD-EFFECT TRANSISTORS In a field-effect-transistor (Fig. S1(a)), current flows through a semiconducting
Supporting Information
Supporting Information Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits Yuanda Liu, and Kah-Wee Ang* Department of Electrical and Computer Engineering National University
Analysis of Transconductances in Deep Submicron CMOS with EKV 3.0
MOS Models & Parameter Extraction Workgroup Arbeitskreis MOS Modelle & Parameterextraktion XFAB, Erfurt, Germany, October 2, 2002 Analysis of Transconductances in Deep Submicron CMOS with EKV 3.0 Matthias
6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
ECE-305: Spring 2016 MOSFET IV
ECE-305: Spring 2016 MOSFET IV Professor Mark Lundstrom Electrical and Computer Engineering Purdue University, West Lafayette, IN USA lundstro@purdue.edu Lundstrom s lecture notes: Lecture 4 4/7/16 outline
Nanoscale CMOS Design Issues
Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal
MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.
INEL 6055 - Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ
Extensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
The Prospects for III-Vs
10 nm CMOS: The Prospects for III-Vs J. A. del Alamo, Dae-Hyun Kim 1, Donghyun Jin, and Taewoo Kim Microsystems Technology Laboratories, MIT 1 Presently with Teledyne Scientific 2010 European Materials
Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed