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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects MOS Physics Cutoff Depletion Inversion Penn ESE 570 Spring 019 Khanna CMOS Layers Example: NAND Gate (Horizontal) Standard nwell Process Active (Diffusion) (Drain/Source regions) Polysilicon (Gate Terminals) Metal 1, Metal, Metal3 Poly Contact (connects metal 1 to polysilicon) Active Contact (connects metal 1 to active) Via (connects metal to metal 1) nwell (PMOS bulk region) n Select (used with active to create ntype diffusion) p Select (used with active to create ptype diffusion) 3 4 Standard Cells Standard Cell Area Lay out gates so that heights match Rows of adjacent cells Standardized sizes Motivation: automated place and route EDA tools convert HDL to layout inv nand3 All cells uniform height Cell area Width of channel determined by routing 5 6 1

2 Standard Cell Layout Example Standard Cell Layout Example CMOS Layers CMOS Process Enhancements Standard nwell Process Interconnect Active (Diffusion) (Drain/Source regions) Polysilicon (Gate Terminals) Metal 1, Metal, Metal3 Poly Contact (connects metal 1 to polysilicon) Active Contact (connects metal 1 to active) Via (connects metal to metal 1) nwell (PMOS bulk region) n Select (used with active to create ntype diffusion) p Select (used with active to create ptype diffusion) 9 Interconnect Cross Section 8 Metal Interconnect (up to 8 metal levels) Copper Interconnect (upper two or more levels) Polysilicon (two or more levels, also for high quality capacitors) Stacked contacts and vias 10 Local Interconnect ITRS ITRS 007 1

3 CMOS Process Enhancements Interconnect Metal Interconnect (up to 8 metal levels) Copper Interconnect (upper two or more levels) Polysilicon (two or more levels, also for high quality capacitors) Stacked contacts and vias Circuit Elements Resistors Capacitors BJTs CMOS PolyPoly Capacitors W L Resistors CMOS Process Enhancements Interconnect Metal Interconnect (up to 8 metal levels) Copper Interconnect (upper two or more levels) Polysilicon (two or more levels, also for high quality capacitors) Stacked contacts and vias Circuit Elements Resistors Capacitors BJTs Devices Multiple thresholds (High and low V t ) Highk gate dielectrics FinFET HighK dielectric HighK dielectric Survey SiO Dielectric Poly gate MOSFET HighK Dielectric Metal gate MOSFET Dielectric constant=3.9 Dielectric constant=0 17 Wong/IBM J. of R&D, V46N/3P ,

4 nm 3D FinFET Transistor CMOS Process Enhancements Interconnect Circuit Elements Resistors Capacitors BJTs Highk TriGate transistors with multiple gate fins connected together dielectric increases total drive strength for Devices higher performance Metal Interconnect (up to 8 metal levels) Copper Interconnect (upper two or more levels) Polysilicon (two or more levels, also for high quality capacitors) Stacked contacts and vias Multiple thresholds (High and low Vt) Highk gate dielectrics FinFET Silicon on insulator process (SOI) Fabricate on insulator for high speed/low leakage SOI Technology Semiconductor Physics SOIbased devices differ from conventional silicon built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide of sapphire 1 Silicon Lattice Energy State View Cartoon twodimensional view Energy Valance Band all states filled 3 4 4

5 Energy State View Energy State View Conduction Band all states empty Conduction Band all states empty Energy Energy Band Gap Valance Band all states filled Valance Band all states filled 5 6 Band Gap and Conduction Doping Insulator 8ev E c Metal OR E c E v Add impurities to Silicon Lattice Replace a Si atom at a lattice site with another E.g. add a Group 15 element E.g. P (Phosphorus) E v E v E c Semiconductor 1.1ev E c E v 7 8 Doping with P (ntype) Doped Band Gaps End up with extra electrons Donor electrons Not tightly bound to atom Low energy to displace Easy for these electrons to move Addition of donor electrons makes more metallic Easier to conduct Semiconductor 0.045ev 1.1ev E c E D E v

6 Doping with B (ptype) End up with electron vacancies Holes Acceptor electron sites Easy for electrons to shift into these sites Low energy to displace Easy for the electrons to move Movement of an electron best viewed as movement of hole Doped Band Gaps Addition of acceptor sites makes more metallic Easier to conduct Semiconductor E c 0.045ev 1.1ev E A E v 31 3 MOSFETs Donor doping Excess electrons MOS Physics nmos Negative or Ntype material NFET (active regions) MOS capacitor Acceptor doping Excess holes Positive or Ptype material PFET (active regions) 33 TwoTerminal MOS Structure TwoTerminal MOS Structure GATE Si Oxide interface GATE L W Si Oxide interface n+ n+ n+ n

7 TwoTerminal MOS Structure TwoTerminal MOS Structure GATE GATE Si Oxide interface Si Oxide interface n+ n+ n+ n+ Equilibrium (Mass action law) Product of hole and electron densities is constant at equilibrium n 0 p 0 =n i n i =1.45x10 10 cm 3 37 n 0 p 0 =n i n i =1.45x10 10 cm 3 Let (ptype) substrate be uniformly doped with concentration 38 TwoTerminal MOS Structure TwoTerminal MOS Structure GATE Si Oxide interface GATE Si Oxide interface n+ n+ n+ n+ n 0 p 0 =n i n i =1.45x10 10 cm 3 Let (ptype) substrate be uniformly doped with concentration p p0 = # n p0 =n i / 39 n 0 p 0 =n i n i =1.45x10 10 cm 3 Let (ptype) substrate be uniformly doped with concentration p p0 = # n p0 =n i / If Ntype doped substrate: n n0 =N D # p n0 =n i /N D 40 Semiconductor Band Gap Ptype Doped Semiconductor Band Gap Free space Electron affinity of silicon Free space Conduction band Conduction band E i = E C E V Intrinsic Fermi level Intrinsic Fermi level Fermi level Fermi level Valence band Valence band 41 qφ and E are in units of energy = electronvolts (ev); where 1 ev = 1.6 x J. 1 ev corresponds to energy acquired by a free electron that is accelerated by an electric potential of one volt. Φ and V corresponds to potential difference in volts. 4 7

8 Ptype Doped Semiconductor Band Gap MOS Capacitor Energy Bands Free space Conduction band Intrinsic Fermi level Fermi level Valence band Fermi potential: = E E F i Φ q Fp = kt q ln n i MOS System Band Diagram Band Diagram Demo Three components put in physical contact Fermi levels must line up MOS Capacitor with External Bias Three Regions of Operation (w/ V B =0): Accumulation Region V G < 0 Depletion Region V G > 0, small Inversion Region V G, large Accumulation Region Holes Accumulate at the siliconoxide interface Electrons Near surface repelled into silicon bulk Interface accumulated with mobile carriers (holes)

9 Accumulation Region Energy Bands Depletion Region Accumulation V G < 0 E Fm qv G = E Fp E Fm qφ S Si surface Band bending due to V G < 0 qφ(x) q E Fp Holes Near siliconoxide interface repelled into silicon bulk Electrons Left behind at interface 0 x Interface depleted of mobile carriers (holes) Depletion Region Energy Bands Depletion Region Depletion V G > 0 (small) Si surface Band bending due to V G > 0 = Φ F = kt q ln n i < 0 6 mv at room T qφ(x) Φ Φ S Surface potential Bulk potential qv G = E Fp E Fm qφ S q E Fp E Fm x d 0 x 51 5 Depletion Region Depletion Region = Φ F = kt q ln n i < 0 6 mv at room T = Φ F = kt q ln n i < 0 6 mv at room T Φ Φ S Surface potential Bulk potential Φ Φ S Surface potential Bulk potential dq = q dx dφ = x dq Mobile hole charge density (per unit area) in thin layer below surface Potential required to displace dq by distance x dφ = q x dx 53 dφ = Φ S x d = x d 0 q x q dx = q N x A d = 54 9

10 Depletion Region Inversion Region Φ Φ S Surface potential Bulk potential = Φ F = kt q ln n i < 0 6 mv at room T Holes Repelled deeper into silicon bulk Electrons Attracted to siliconoxide interface V G Inversion condition Q = q x d Q = q = q q When Φ S = Φ F Density of mobile electrons at surface = density of mobile carriers in bulk Inversion Region Energy Bands Inversion Region Inversion V G 0 > 0 Si surface Inversion condition V G qv G = E Fp E Fm qφ S q E Fp When Φ S = Φ F Density of mobile electrons at surface = density of mobile carriers in bulk E Fm 0 x dm x Inversion Region Band Diagram Demo Inversion condition When Φ S = Φ F Density of mobile electrons at surface = density of mobile carriers in bulk V G x dm = q = q Q = q = q

11 MOS Capacitor with External Bias terminal MOS Cap # 3terminal nmos Three Regions of Operation: Accumulation Region V G < 0 (Cutoff) Depletion Region V G > 0, small (Subthreshold) Inversion Region V G, large (Above Threshold) V G VS V G V D depletion region Cutoff/Subthreshold Above threshold 61 6 nmos = MOS cap + source/drain For V SB =0, the threshold voltage is denoted as 0 or 0n,p V SB = 0 V S V G V D 0 Φ F Φ GC : Work function difference between gate and channel Metal Gate: Φ GC =Φ F (substrate) Φ M Poly Gate: Φ GC =Φ F (substrate) Φ F (gate) Q OX : Fixed positive charge density at interface Q OX = qn OX C/cm C OX : Gate oxide capacitance per unit area C OX =ε OX / Φ GC : Bulk fermi potential Q B0 : Depletion region charge density at inversion Q B0 = q Φ F For V SB =0, the threshold voltage is denoted as 0 or 0n,p Φ GC : Work function difference between gate and channel Metal Gate: Φ GC =Φ F (substrate) Φ M Poly Gate: Φ GC =Φ F (substrate) Φ F (gate) Q OX : Fixed positive charge density at interface Q OX = qn OX C/cm C OX : Gate oxide capacitance per unit area C OX =ε OX / Φ GC : Bulk fermi potential 0 Φ F Q B0 : Depletion region charge density at inversion for V SB = 0 for V SB = 0 = 0 Φ F Φ F Q B Φ F Q B = 0 Q B Q B0 = q Φ F

12 for V SB = 0 = 0 Φ F for V SB = 0 = 0 Φ F for V SB = 0 Φ F Q B for V SB = 0 Φ F Q B Φ F Q B Φ F Q B γ = 0 Q B Q = q Φ F = 0 Q B Q = q Φ F ( ) Q Q B B0 = q Φ F V SB Φ F ( ) Q Q B B0 = q Φ F V SB Φ F = 0 +γ ( Φ F V SB Φ F ) = 0 +γ ( Φ F V SB Φ F ) Examples 3. and 3.3 in text (pp ) Be careful with signs Nchannel Pchannel ϕ F negative positive Q B0,Q B negative positive ϒ positive negative V SB positive (0n ) negative (0p ) Big Idea 3 operating regions Cutoff Depletion Inversion Threshold voltage Defined by onset of inversion Doping and V SB change V SB

13 Admin HW due Friday, /1 Submit in canvas 73 13

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