Lecture 37: Frequency response. Context

Size: px
Start display at page:

Download "Lecture 37: Frequency response. Context"

Transcription

1 EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will do a review of the approximate frequency analysis of circuits which have a single dominant pole.

2 EECS 05 Spring 004, Lecture 37 Reading Chapter 0, Frequency analysis of active circuits EECS 05 Spring 004, Lecture 37 Lecture Outline Finish Example: CS NMOS->CS PMOS amplifier Review of frequency analysis (with a dominant pole)

3 EECS 05 Spring 004, Lecture 37 Multistage Amplifier Design Example Start with basic two-stage transconductance amplifier: Why do this combination? EECS 05 Spring 004, Lecture 37 Quiescent level shifts CS NMOS (typical) PMOS (typical) CG CD Source follower (known shift) (known shift) 3

4 EECS 05 Spring 004, Lecture 37 CS CS Amplifier Direct DC connection: use NMOS then PMOS EECS 05 Spring 004, Lecture 37 Current Supply Design Assume that the reference is a sink set by a resistor Must mirror the reference current and generate a sink for i SUP 4

5 EECS 05 Spring 004, Lecture 37 Use Basic Current Supplies EECS 05 Spring 004, Lecture 37 Complete Amplifier Topology What s missing? The device dimensions, the bias voltage and reference resistor 5

6 EECS 05 Spring 004, Lecture 37 DC Bias: Find Operating Points Find V BIAS such that V OUT 0 V Device parameters: µ 50 µa/v µ 5 µa/v n C ox V Tn V pc ox V Tp - V λ n 0.05 V - λ p 0.05 V - Device dimensions (for lecture design): (W/L) n 50/ (W/L) p 80/ EECS 05 Spring 004, Lecture 37 Finding R REF V Require I REF - I D3 50 µa M 3 V SG3 V Tp I D3 µ C ( W / L) p ox 3 R REF 50µ A 4 V SG 3 ( ) V. 3V 5µ A(80 / ) 40 V - I A [ V V ] [ V ] SG3 REF 50µ Rref [.5.3] [.5] 50µ A Rref 74kΩ R ref 6

7 EECS 05 Spring 004, Lecture 37 DC Operating Point I REF 50 µa V BIAS V V I D µ C ( W / L) 00µ A 50( µ A/ V )(50 / ) GS tn n ox 9 V 7 EECS 05 Spring 004, Lecture 37 Small-Signal Device Parameters Transistors M and M g m 350 µs r o 400 kω g m 35 µs r o 400 kω Current supplies i SUP and i SUP r oc r o4 400 kω r oc r o6 400 kω 7

8 EECS 05 Spring 004, Lecture 37 Two-Port Model Find G m i out / v in EECS 05 Spring 004, Lecture 37 Output Voltage Swing Transistors M and M 6 will limit the output swing 8

9 EECS 05 Spring 004, Lecture 37 Limits to Output Voltage M 6 will leave saturation when v OUT drops to: OUT, MIN V v V DS 6, sat.5 I µ C n ox D6 v OUT,MIN V M will leave saturation when v OUT rises to: OUT, MAX V v V SD, sat.5 v OUT,MAX V What about M 4? ( I µ C p ox ( W / L) 6 D ) ( W / L) EECS 05 Spring 004, Lecture 37 Output Current Swing Load resistor: pick R L 5 kω Output current: i v / R OUT OUT L i OUT i OUT i ( i ) D6 D Limits: asymmetrical v OUT M : can increase - i D M 6 : can t increase i D6 9

10 EECS 05 Spring 004, Lecture 37 Output Current Limits Positive output current (negative v OUT ) ( 0 ) 50 A vout, MIN RL i / OUT, MAX id6 µ vout, MIN (50µ A)(5kΩ). 5V (less negative than limit set by saturation of M 6 ) Negative output current (positive v OUT ) No limit on current from M, so voltage swing sets current limit i OUT, MIN v OUT, MAX / R (.8V / 5kΩ) 87.µ A L EECS 05 Spring 004, Lecture 37 Transfer Curves (for R L 5 kω) Loaded voltage gain v out /v in (g m R out )(g m R out R L ) 490 Loaded transconductance i out /v in (-g m R out )(g m )(R out /(R out R L ) -9.5 ms v OUT i OUT [µa] v IN v IN 0

11 EECS 05 Spring 004, Lecture 37 Frequency response The frequency response of single stage transistor CS voltage amplifiers can be modeled with the following small signal model. We have approximated the frequency response by using the Miller approximation and assuming a single dominant pole. v C gd C g v m in ro v out EECS 05 Spring 004, Lecture 37 Phasor analysis As an example problem, we will review the Miller/Dominant pole approximation for this circuit, and phasor analysis, and compare the results C gd v C g v m in ro v out Using the Miller approximation, we replaced C with a capacitance C M to ground, where: M ( ( g m R L r o ) C C ) A 0

12 EECS 05 Spring 004, Lecture 37 Phasor analysis C gd v C g v m in ro v out Let s take a look at this as a frequency analysis problem. Since this is a linear circuit, we can drive the circuit at a single frequency ω, and find the voltages at any node and currents through any wire in the circuit in terms of their amplitude and phase. EECS 05 Spring 004, Lecture 37 Defining the phasors We now define the phasors: i v v in out ( ˆ jωt I e C. C. ) in ( ˆ jωt V e C. C. ) in ( ˆ jωt V e C. C. ) out Etc.

13 EECS 05 Spring 004, Lecture 37 Phasor analysis C gd v C g v m in ro The current into the capacitor C is: ( ) d Iin( t) Cgd V ( t) Vout ( t) dt Plugging in our phasors, we have: { Iˆ C. C. } { jωc ( Vˆ Vˆ ) C. C. } in gd out v out EECS 05 Spring 004, Lecture 37 Phasor analysis C gd Dropping the ½ s and the C.C. s we switch to phasor notation: Iˆ jωc Vˆ Vˆ If we look at the currents in and out of the output node: ˆ Vˆ out g ( ˆ ˆ ) 0 mv Vout V jωc r R v C in o g v m in L gd ro ( ) out v out R L 3

14 EECS 05 Spring 004, Lecture 37 ˆ Vˆ out g ( ˆ ˆ ) 0 mv Vout V jωc r R o L We can the solve for V out in terms of V in, which is the small signal gain at the frequency ω: Vˆ Vˆ out A( jω) g m ( R r ) g jω C jω L ( R r ) If we plug this value for A into the equation: Iˆ jωc Vˆ Vˆ L in 0 gd m 0 C ( ) out EECS 05 Spring 004, Lecture 37 We find: Iˆ in jωc gd ( A( jω) ) Vˆ The Miller approximation takes: Why does this work? It s because the current feeding the capacitance is a high impedance source, and the response of that RC time is what limits the performance of the circuit (usually). Since: A0 g m ( R L r0 ) C M ( g m ( R L r0 )) C gd A( jω) A 0 4

15 EECS 05 Spring 004, Lecture 37 Frequency response ~ R S v C gd C g v m in ro v out RL ~ R S v C C M g v m in ro v out R L EECS 05 Spring 004, Lecture 37 The voltage Vˆ can be found from the input voltage by the impedance divider: Vˆ ( jω( C CM )) Vˆ in Vˆ ( jω( C C )) R ( jω( C C )) in RS M Vˆ ( ) ( ) out gm RL r0 Vˆ RS jω( C CM ) in We now want to write this as: A( jω) K jω p S M 5

16 EECS 05 Spring 004, Lecture 37 Comparing the two, we see: K g m ( R ) L r 0 p R S ( C C ) M The frequency where the gain is down 3 db from its low frequency value occurs when: jω p R S ( C C ) R ( C g ( R r ) C ) M S m L 0 gd EECS 05 Spring 004, Lecture 37 Comparison with exact analysis The exact analysis of the CS circuit proceeds with nodal analysis, without using the Miller approximation. The Miller approximation turns out to be good up to well above the 3 db frequency because of the limitation of the source resistance into the effectively amplified C gd capacitance. 6

17 EECS 05 Spring 004, Lecture 37 Frequency Response of Amplifiers We have a systematic technique to study amplifier performance (derive transfer function, study poles/zeros/bode plots). We have a good qualitative understanding of circuit performance (e.g., CS suffers from Miller effect, CD and CG are wideband stages ) Open Circuit Time Constants: An analytical technique capable of estimating frequency response in the case of amplifiers dominated by a single pole. EECS 05 Spring 004, Lecture 37 The Special Case The transfer function can have no zeroes and must have a dominant pole ω << ω, ω 3,, ω n H ( jω) H o 3 ( jωb ( jω) b ( jω) b...) 3 Factor denominator: H ( jω) H ( jω / ω )( jω / ω )...( jω / ω ) o n 7

18 EECS 05 Spring 004, Lecture 37 Approximating the Transfer Function Multiply out denominator: H ( jω) H ( jω / ω )( jω / ω )...( jω / ω ) o H o jω... ω ω ωn Since ω << ω, ω 3,, ω n n b ω ω... ω n ω EECS 05 Spring 004, Lecture 37 How to Find b? See P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits (EE 40) for derivation Result: b is the sum of open-circuit time constants τ i which can be found by considering each capacitor C i in the amplifier separately and finding the Thévenin resistance R Ti of the network from the capacitor s point of view τ i R Ti C i b n R i TiCi ω n i R Ti C i 8

19 EECS 05 Spring 004, Lecture 37 Finding the Thévenin Resistance Open-circuit all capacitors (i.e.; remove them), except for the coupling capacitors (short them) For capacitor Ci, find the resistance RTi across its terminals with all independent sources removed (voltages shorted, currents opened) might need to apply a test voltage and find the current in some cases. Insight for design: the bandwidth of the amplifier will be limited by the capacitor that contributes the largest τ i RT i C i not necessarily the largest C i 9

The Miller Approximation

The Miller Approximation The Miller Approximation The exact analysis is not particularly helpful for gaining insight into the frequency response... consider the effect of C µ on the input only I t C µ V t g m V t R'out = r o r

More information

I. Frequency Response of Voltage Amplifiers

I. Frequency Response of Voltage Amplifiers I. Frequency Response of Voltage Amplifiers A. Common-Emitter Amplifier: V i SUP i OUT R S V BIAS R L v OUT V Operating Point analysis: 0, R s 0, r o --->, r oc --->, R L ---> Find V BIAS such that I C

More information

Multistage Amplifier Frequency Response

Multistage Amplifier Frequency Response Multistage Amplifier Frequency Response * Summary of frequency response of single-stages: CE/CS: suffers from Miller effect CC/CD: wideband -- see Section 0.5 CB/CG: wideband -- see Section 0.6 (wideband

More information

Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller

Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller EECS 105 Spring 2017, Module 4 Frequency Response Prof. Ali M. Niknejad Department of EECS Announcements l HW9 due on Friday 2 Review: CD with Current Mirror 3 Review: CD with Current Mirror 4 Review:

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

More information

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.

Assignment 3 ELEC 312/Winter 12 R.Raut, Ph.D. Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT-3 Department of Electrical and Computer Engineering Winter 2012 1. A common-emitter amplifier that can be represented by the following equivalent circuit,

More information

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH) EE05 Fall 205 Microelectronic Devices and Circuits Frequency Response Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Amplifier Frequency Response: Lower and Upper Cutoff Frequency Midband

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

ECEN 326 Electronic Circuits

ECEN 326 Electronic Circuits ECEN 326 Electronic Circuits Frequency Response Dr. Aydın İlker Karşılayan Texas A&M University Department of Electrical and Computer Engineering High-Frequency Model BJT & MOS B or G r x C f C or D r

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multi-stage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

Exact Analysis of a Common-Source MOSFET Amplifier

Exact Analysis of a Common-Source MOSFET Amplifier Exact Analysis of a Common-Source MOSFET Amplifier Consider the common-source MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel

More information

Lecture 04: Single Transistor Ampliers

Lecture 04: Single Transistor Ampliers Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37 Single-Transistor

More information

EECS 105: FALL 06 FINAL

EECS 105: FALL 06 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

More information

ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture 11 MOS Amplifiers ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

More information

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of

More information

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.

More information

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005 6.02 Microelectronic Devices and Circuits Fall 2005 Lecture 23 Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier December, 2005 Contents:. Introduction 2. Intrinsic frequency response

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

Stability and Frequency Compensation

Stability and Frequency Compensation 類比電路設計 (3349) - 2004 Stability and Frequency ompensation hing-yuan Yang National hung-hsing University Department of Electrical Engineering Overview Reading B Razavi hapter 0 Introduction In this lecture,

More information

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

Refinements to Incremental Transistor Model

Refinements to Incremental Transistor Model Refinements to Incremental Transistor Model This section presents modifications to the incremental models that account for non-ideal transistor behavior Incremental output port resistance Incremental changes

More information

CMOS Analog Circuits

CMOS Analog Circuits CMOS Analog Circuits L6: Common Source Amplifier-1 (.8.13) B. Mazhari Dept. of EE, IIT Kanpur 19 Problem statement : Design an amplifier which has the following characteristics: + CC O in R L - CC A 100

More information

ECE 6412, Spring Final Exam Page 1

ECE 6412, Spring Final Exam Page 1 ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.

More information

Advanced Current Mirrors and Opamps

Advanced Current Mirrors and Opamps Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------

More information

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3 ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

More information

EECS 141: FALL 05 MIDTERM 1

EECS 141: FALL 05 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

More information

LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter

LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH ) Trip Point of an Inverter Lecture 380 Two-Stage Open-Loop Comparators-II (4/5/02) Page 380-1 LECTURE 380 TWO-STAGE OPEN-LOOP COMPARATORS - II (READING: AH 445-461) Trip Point of an Inverter V DD In order to determine the propagation

More information

EE105 Fall 2014 Microelectronic Devices and Circuits

EE105 Fall 2014 Microelectronic Devices and Circuits EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam

More information

Chapter 9 Frequency Response. PART C: High Frequency Response

Chapter 9 Frequency Response. PART C: High Frequency Response Chapter 9 Frequency Response PART C: High Frequency Response Discrete Common Source (CS) Amplifier Goal: find high cut-off frequency, f H 2 f H is dependent on internal capacitances V o Load Resistance

More information

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output

More information

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

EE 321 Analog Electronics, Fall 2013 Homework #8 solution

EE 321 Analog Electronics, Fall 2013 Homework #8 solution EE 321 Analog Electronics, Fall 2013 Homework #8 solution 5.110. The following table summarizes some of the basic attributes of a number of BJTs of different types, operating as amplifiers under various

More information

Lecture 23 - Frequency Resp onse of Amplifiers (I) Common-Source Amplifier. May 6, 2003

Lecture 23 - Frequency Resp onse of Amplifiers (I) Common-Source Amplifier. May 6, 2003 6.0 Microelectronic Devices and Circuits Spring 003 Lecture 3 Lecture 3 Frequency Resp onse of Amplifiers (I) CommonSource Amplifier May 6, 003 Contents:. Intro duction. Intrinsic frequency resp onse of

More information

Lecture Stage Frequency Response - I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E.

Lecture Stage Frequency Response - I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E. Lecture 070 Stage Frequency esponse I (/0/0) Page 070 LECTUE 070 SINGLESTAGE FEQUENCY ESPONSE I (EADING: GHLM 488504) Objective The objective of this presentation is:.) Illustrate the frequency analysis

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

Systematic Design of Operational Amplifiers

Systematic Design of Operational Amplifiers Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 061 Table of contents Design of Single-stage OTA Design of

More information

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

More information

1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)

1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn

More information

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1 Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced

More information

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130 ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED

More information

Integrated Circuit Operational Amplifiers

Integrated Circuit Operational Amplifiers Analog Integrated Circuit Design A video course under the NPTEL Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India National Programme on Technology Enhanced

More information

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14 Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Lecture 06: Current Mirrors

Lecture 06: Current Mirrors Lecture 06: Current Mirrors Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture VI 1 / 26 Lowered Resistance Looking into

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

Lecture 28 Field-Effect Transistors

Lecture 28 Field-Effect Transistors Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent

More information

Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

The current source. The Active Current Source

The current source. The Active Current Source V ref + - The current source Minimum noise euals: Thevenin Norton = V ref DC current through resistor gives an increase of /f noise (granular structure) Accuracy of source also determined by the accuracy

More information

ECE315 / ECE515 Lecture 11 Date:

ECE315 / ECE515 Lecture 11 Date: ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)

More information

Electronics II. Final Examination

Electronics II. Final Examination The University of Toledo f17fs_elct27.fm 1 Electronics II Final Examination Problems Points 1. 11 2. 14 3. 15 Total 40 Was the exam fair? yes no The University of Toledo f17fs_elct27.fm 2 Problem 1 11

More information

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 =

ECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION - SOLUTIONS (Average score = 78/100) R 2 = R 1 = ECE 3050A, Spring 2004 Page Problem (20 points This problem must be attempted) The simplified schematic of a feedback amplifier is shown. Assume that all transistors are matched and g m ma/v and r ds.

More information

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers

Electronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers 6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,

More information

Sinusoidal Steady State Analysis (AC Analysis) Part I

Sinusoidal Steady State Analysis (AC Analysis) Part I Sinusoidal Steady State Analysis (AC Analysis) Part I Amin Electronics and Electrical Communications Engineering Department (EECE) Cairo University elc.n102.eng@gmail.com http://scholar.cu.edu.eg/refky/

More information

At point G V = = = = = = RB B B. IN RB f

At point G V = = = = = = RB B B. IN RB f Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F

More information

Lecture 140 Simple Op Amps (2/11/02) Page 140-1

Lecture 140 Simple Op Amps (2/11/02) Page 140-1 Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and

More information

Voltage AmpliÞer Frequency Response

Voltage AmpliÞer Frequency Response Voltage AmpliÞer Frequency Response Chapter 9 multistage voltage ampliþer 5 V M 7B M 7 M 5 R 35 kω M 6B M 6 Q 4 100 µa X M 3 Q B Q v OUT V s M 1 M 8 M9 V BIAS M 10 Approaches: 1. brute force OCTC -- do

More information

Transistor amplifiers: Biasing and Small Signal Model

Transistor amplifiers: Biasing and Small Signal Model Transistor amplifiers: iasing and Small Signal Model Transistor amplifiers utilizing JT or FT are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly. Then, similar FT

More information

CE/CS Amplifier Response at High Frequencies

CE/CS Amplifier Response at High Frequencies .. CE/CS Amplifier Response at High Frequencies INEL 4202 - Manuel Toledo August 20, 2012 INEL 4202 - Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3

More information

Section 1: Common Emitter CE Amplifier Design

Section 1: Common Emitter CE Amplifier Design ECE 3274 BJT amplifier design CE, CE with Ref, and CC. Richard Cooper Section 1: CE amp Re completely bypassed (open Loop) Section 2: CE amp Re partially bypassed (gain controlled). Section 3: CC amp (open

More information

55:041 Electronic Circuits The University of Iowa Fall Final Exam

55:041 Electronic Circuits The University of Iowa Fall Final Exam Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Lecture 12 CMOS Delay & Transient Response

Lecture 12 CMOS Delay & Transient Response EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

More information

Frequency Response. Re ve jφ e jωt ( ) where v is the amplitude and φ is the phase of the sinusoidal signal v(t). ve jφ

Frequency Response. Re ve jφ e jωt ( ) where v is the amplitude and φ is the phase of the sinusoidal signal v(t). ve jφ 27 Frequency Response Before starting, review phasor analysis, Bode plots... Key concept: small-signal models for amplifiers are linear and therefore, cosines and sines are solutions of the linear differential

More information

Chapter 10 Feedback. PART C: Stability and Compensation

Chapter 10 Feedback. PART C: Stability and Compensation 1 Chapter 10 Feedback PART C: Stability and Compensation Example: Non-inverting Amplifier We are analyzing the two circuits (nmos diff pair or pmos diff pair) to realize this symbol: either of the circuits

More information

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

More information

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First

More information

Amplifiers, Source followers & Cascodes

Amplifiers, Source followers & Cascodes Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 0-05 02 Operational amplifier Differential pair v- : B v + Current mirror

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open

More information

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013. Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

More information

Introduction to AC Circuits (Capacitors and Inductors)

Introduction to AC Circuits (Capacitors and Inductors) Introduction to AC Circuits (Capacitors and Inductors) Amin Electronics and Electrical Communications Engineering Department (EECE) Cairo University elc.n102.eng@gmail.com http://scholar.cu.edu.eg/refky/

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg

Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1

Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1 Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information