# Lecture 37: Frequency response. Context

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1 EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will do a review of the approximate frequency analysis of circuits which have a single dominant pole.

2 EECS 05 Spring 004, Lecture 37 Reading Chapter 0, Frequency analysis of active circuits EECS 05 Spring 004, Lecture 37 Lecture Outline Finish Example: CS NMOS->CS PMOS amplifier Review of frequency analysis (with a dominant pole)

3 EECS 05 Spring 004, Lecture 37 Multistage Amplifier Design Example Start with basic two-stage transconductance amplifier: Why do this combination? EECS 05 Spring 004, Lecture 37 Quiescent level shifts CS NMOS (typical) PMOS (typical) CG CD Source follower (known shift) (known shift) 3

4 EECS 05 Spring 004, Lecture 37 CS CS Amplifier Direct DC connection: use NMOS then PMOS EECS 05 Spring 004, Lecture 37 Current Supply Design Assume that the reference is a sink set by a resistor Must mirror the reference current and generate a sink for i SUP 4

5 EECS 05 Spring 004, Lecture 37 Use Basic Current Supplies EECS 05 Spring 004, Lecture 37 Complete Amplifier Topology What s missing? The device dimensions, the bias voltage and reference resistor 5

6 EECS 05 Spring 004, Lecture 37 DC Bias: Find Operating Points Find V BIAS such that V OUT 0 V Device parameters: µ 50 µa/v µ 5 µa/v n C ox V Tn V pc ox V Tp - V λ n 0.05 V - λ p 0.05 V - Device dimensions (for lecture design): (W/L) n 50/ (W/L) p 80/ EECS 05 Spring 004, Lecture 37 Finding R REF V Require I REF - I D3 50 µa M 3 V SG3 V Tp I D3 µ C ( W / L) p ox 3 R REF 50µ A 4 V SG 3 ( ) V. 3V 5µ A(80 / ) 40 V - I A [ V V ] [ V ] SG3 REF 50µ Rref [.5.3] [.5] 50µ A Rref 74kΩ R ref 6

7 EECS 05 Spring 004, Lecture 37 DC Operating Point I REF 50 µa V BIAS V V I D µ C ( W / L) 00µ A 50( µ A/ V )(50 / ) GS tn n ox 9 V 7 EECS 05 Spring 004, Lecture 37 Small-Signal Device Parameters Transistors M and M g m 350 µs r o 400 kω g m 35 µs r o 400 kω Current supplies i SUP and i SUP r oc r o4 400 kω r oc r o6 400 kω 7

8 EECS 05 Spring 004, Lecture 37 Two-Port Model Find G m i out / v in EECS 05 Spring 004, Lecture 37 Output Voltage Swing Transistors M and M 6 will limit the output swing 8

9 EECS 05 Spring 004, Lecture 37 Limits to Output Voltage M 6 will leave saturation when v OUT drops to: OUT, MIN V v V DS 6, sat.5 I µ C n ox D6 v OUT,MIN V M will leave saturation when v OUT rises to: OUT, MAX V v V SD, sat.5 v OUT,MAX V What about M 4? ( I µ C p ox ( W / L) 6 D ) ( W / L) EECS 05 Spring 004, Lecture 37 Output Current Swing Load resistor: pick R L 5 kω Output current: i v / R OUT OUT L i OUT i OUT i ( i ) D6 D Limits: asymmetrical v OUT M : can increase - i D M 6 : can t increase i D6 9

10 EECS 05 Spring 004, Lecture 37 Output Current Limits Positive output current (negative v OUT ) ( 0 ) 50 A vout, MIN RL i / OUT, MAX id6 µ vout, MIN (50µ A)(5kΩ). 5V (less negative than limit set by saturation of M 6 ) Negative output current (positive v OUT ) No limit on current from M, so voltage swing sets current limit i OUT, MIN v OUT, MAX / R (.8V / 5kΩ) 87.µ A L EECS 05 Spring 004, Lecture 37 Transfer Curves (for R L 5 kω) Loaded voltage gain v out /v in (g m R out )(g m R out R L ) 490 Loaded transconductance i out /v in (-g m R out )(g m )(R out /(R out R L ) -9.5 ms v OUT i OUT [µa] v IN v IN 0

11 EECS 05 Spring 004, Lecture 37 Frequency response The frequency response of single stage transistor CS voltage amplifiers can be modeled with the following small signal model. We have approximated the frequency response by using the Miller approximation and assuming a single dominant pole. v C gd C g v m in ro v out EECS 05 Spring 004, Lecture 37 Phasor analysis As an example problem, we will review the Miller/Dominant pole approximation for this circuit, and phasor analysis, and compare the results C gd v C g v m in ro v out Using the Miller approximation, we replaced C with a capacitance C M to ground, where: M ( ( g m R L r o ) C C ) A 0

12 EECS 05 Spring 004, Lecture 37 Phasor analysis C gd v C g v m in ro v out Let s take a look at this as a frequency analysis problem. Since this is a linear circuit, we can drive the circuit at a single frequency ω, and find the voltages at any node and currents through any wire in the circuit in terms of their amplitude and phase. EECS 05 Spring 004, Lecture 37 Defining the phasors We now define the phasors: i v v in out ( ˆ jωt I e C. C. ) in ( ˆ jωt V e C. C. ) in ( ˆ jωt V e C. C. ) out Etc.

13 EECS 05 Spring 004, Lecture 37 Phasor analysis C gd v C g v m in ro The current into the capacitor C is: ( ) d Iin( t) Cgd V ( t) Vout ( t) dt Plugging in our phasors, we have: { Iˆ C. C. } { jωc ( Vˆ Vˆ ) C. C. } in gd out v out EECS 05 Spring 004, Lecture 37 Phasor analysis C gd Dropping the ½ s and the C.C. s we switch to phasor notation: Iˆ jωc Vˆ Vˆ If we look at the currents in and out of the output node: ˆ Vˆ out g ( ˆ ˆ ) 0 mv Vout V jωc r R v C in o g v m in L gd ro ( ) out v out R L 3

14 EECS 05 Spring 004, Lecture 37 ˆ Vˆ out g ( ˆ ˆ ) 0 mv Vout V jωc r R o L We can the solve for V out in terms of V in, which is the small signal gain at the frequency ω: Vˆ Vˆ out A( jω) g m ( R r ) g jω C jω L ( R r ) If we plug this value for A into the equation: Iˆ jωc Vˆ Vˆ L in 0 gd m 0 C ( ) out EECS 05 Spring 004, Lecture 37 We find: Iˆ in jωc gd ( A( jω) ) Vˆ The Miller approximation takes: Why does this work? It s because the current feeding the capacitance is a high impedance source, and the response of that RC time is what limits the performance of the circuit (usually). Since: A0 g m ( R L r0 ) C M ( g m ( R L r0 )) C gd A( jω) A 0 4

15 EECS 05 Spring 004, Lecture 37 Frequency response ~ R S v C gd C g v m in ro v out RL ~ R S v C C M g v m in ro v out R L EECS 05 Spring 004, Lecture 37 The voltage Vˆ can be found from the input voltage by the impedance divider: Vˆ ( jω( C CM )) Vˆ in Vˆ ( jω( C C )) R ( jω( C C )) in RS M Vˆ ( ) ( ) out gm RL r0 Vˆ RS jω( C CM ) in We now want to write this as: A( jω) K jω p S M 5

16 EECS 05 Spring 004, Lecture 37 Comparing the two, we see: K g m ( R ) L r 0 p R S ( C C ) M The frequency where the gain is down 3 db from its low frequency value occurs when: jω p R S ( C C ) R ( C g ( R r ) C ) M S m L 0 gd EECS 05 Spring 004, Lecture 37 Comparison with exact analysis The exact analysis of the CS circuit proceeds with nodal analysis, without using the Miller approximation. The Miller approximation turns out to be good up to well above the 3 db frequency because of the limitation of the source resistance into the effectively amplified C gd capacitance. 6

17 EECS 05 Spring 004, Lecture 37 Frequency Response of Amplifiers We have a systematic technique to study amplifier performance (derive transfer function, study poles/zeros/bode plots). We have a good qualitative understanding of circuit performance (e.g., CS suffers from Miller effect, CD and CG are wideband stages ) Open Circuit Time Constants: An analytical technique capable of estimating frequency response in the case of amplifiers dominated by a single pole. EECS 05 Spring 004, Lecture 37 The Special Case The transfer function can have no zeroes and must have a dominant pole ω << ω, ω 3,, ω n H ( jω) H o 3 ( jωb ( jω) b ( jω) b...) 3 Factor denominator: H ( jω) H ( jω / ω )( jω / ω )...( jω / ω ) o n 7

18 EECS 05 Spring 004, Lecture 37 Approximating the Transfer Function Multiply out denominator: H ( jω) H ( jω / ω )( jω / ω )...( jω / ω ) o H o jω... ω ω ωn Since ω << ω, ω 3,, ω n n b ω ω... ω n ω EECS 05 Spring 004, Lecture 37 How to Find b? See P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits (EE 40) for derivation Result: b is the sum of open-circuit time constants τ i which can be found by considering each capacitor C i in the amplifier separately and finding the Thévenin resistance R Ti of the network from the capacitor s point of view τ i R Ti C i b n R i TiCi ω n i R Ti C i 8

19 EECS 05 Spring 004, Lecture 37 Finding the Thévenin Resistance Open-circuit all capacitors (i.e.; remove them), except for the coupling capacitors (short them) For capacitor Ci, find the resistance RTi across its terminals with all independent sources removed (voltages shorted, currents opened) might need to apply a test voltage and find the current in some cases. Insight for design: the bandwidth of the amplifier will be limited by the capacitor that contributes the largest τ i RT i C i not necessarily the largest C i 9

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