ECE 342 Solid State Devices & Circuits 4. CMOS


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1 ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois ECE 34 Jose Schutt Aine 1
2 Digital Circuits V IH : Input voltage at high state V IHmin V IL : Input voltage at low state V ILmax V OH : Output voltage at high state V OHmin V OL : Output voltage at low state V OLmin Likewise for current we can define Currents into input Currents into output I IH I IHmax I IL I ILmax I OH I OHmax I OL I OLmax ECE 34 Jose Schutt Aine
3 Voltage Transfer Characteristics (VTC) The static operation of a logic circuit is determined by its VTC In low state: noise margin is NM L NM V V L IL OL In high state: noise margin is NM H NM V V H OH IH An ideal VTC will maximize noise margins NM L NM H V IL and V IH are the points where the slope of the VTC=1 Optimum: NM NM V L H DD / ECE 34 Jose Schutt Aine 3
4 Switching Time & Propagation Delay input output ECE 34 Jose Schutt Aine 4
5 Switching Time & Propagation Delay t r =rise time (from 10% to 90%) t f =fall time (from 90% to 10%) t plh =lowtohigh propagation delay t phl =hightolow propagation delay Inverter propagation delay: t p tplh tphl 1 ECE 34 Jose Schutt Aine 5
6 For a logiccircuit family employing a 3V supply, suggest an ideal set of values for V th, V IL, V IH, V OH, NM L, NM H. Also, sketch the VTC. What value of voltage gain in the transition region does your ideal specification imply? Ideal 3V logic implies: V V 3.0 V; V 0.0V OH DD OL V V /3.0/1.5 V; th DD VTC and Noise Margins V V /1.5 V; V V /1.5V IL DD IH DD ECE 34 Jose Schutt Aine 6
7 VTC and Noise Margins NM V V V H OH IH NM V V V L IL OL The gain in the transition region is: V V / V V / OH OL IH IL Inverting transfer characteristics 3/0 V / V ECE 34 Jose Schutt Aine 7
8 CMOS Noise Margins When inverter threshold is at V DD /, the noise margin NM H and NM L are equalized 3 NM NM V V 8 3 H L DD th : noise margin for high input NM L : noise margin for low input V th : threshold voltage Noise margins are typically around 0.4 V DD ; close to half powersupply voltage CMOS ideal from noiseimmunity standpoint ECE 34 Jose Schutt Aine 8
9 Switching Circuit ECE 34 Jose Schutt Aine 9
10 Nonideal Switch R sc Vlow V1 R sc V so R high V 1 L R R so L R ECE 34 Jose Schutt Aine 10
11 IV Characteristics of Switches Ideal switch Nonideal switch ECE 34 Jose Schutt Aine 11
12 Complementary Switches R V sc low V 1 R R sc so R V so high V 1 R R so sc ECE 34 Jose Schutt Aine 1
13 Problem A switch has an open (off) resistance of 10M and close (on) resistance of 100. Calculate the two voltage levels of V out for the circuit shown. Assume R L =5 k V out V R L RS R CC S Open R V V 6 : S 1010 out Short : RS 10 Vout 0.098V ECE 34 Jose Schutt Aine 13
14 Problem If two switches are used as shown, calculate the two output voltage levels. Assume switches are complementary RS on 100, RS off 10 M VCCRS Vout R R S1 S State 1: S 1 off, S on R S1 =10 M, R S = V 5V 0V out State : S 1 on, S off R S1 =100, R S =10 M Vout V ECE 34 Jose Schutt Aine 14
15 MOSFET Switch NMOS PMOS Characteristics of MOS Switch MOS approximates switch better than BJT in off state Resistance in on state can vary from 100 to 1 k ECE 34 Jose Schutt Aine 15
16 NMOS Switch ECE 34 Jose Schutt Aine 16
17 CMOS Switch CMOS switch is called an inverter The body of each device is connected to its source NO BODY EFFECT ECE 34 Jose Schutt Aine 17
18 CMOS Switch Off State OFF State (V in : low) nmos transistor is off Path from V out to V 1 is through PMOS V out : high ECE 34 Jose Schutt Aine 18
19 CMOS Switch Input Low ECE 34 Jose Schutt Aine 19
20 CMOS Switch Input Low GSN NMOS V V OFF TN r dsn high r dsp PMOS 1 k W V V ' p DD TP L p r dsp is low ECE 34 Jose Schutt Aine 0
21 CMOS Switch On State ON State (V in : high) pmos transistor is off Path from V out to ground is through nmos V out : low ECE 34 Jose Schutt Aine 1
22 CMOS Switch Input High ECE 34 Jose Schutt Aine
23 r dsn CMOS Switch Input High NMOS 1 W k V V r dsn is low ' n DD TN L n GSP PMOS V V OFF TP r dsp high ECE 34 Jose Schutt Aine 3
24 CMOS Inverter r dsn 1 k W V V ' N DD T L n r dsp 1 k W V V ' P DD T L p Short switching transient current low power ECE 34 Jose Schutt Aine 4
25 CMOS Inverter Advantages of CMOS inverter Output voltage levels are 0 and V DD signal swing is maximum possible Static power dissipation is zero Low resistance paths to V DD and ground when needed High output driving capability increased speed Input resistance is infinite high fanout Load driving capability of CMOS is high. Transistors can sink or source large load currents that can be used to charge and discharge load capacitances. ECE 34 Jose Schutt Aine 5
26 CMOS Inverter VTC Q P and Q N are matched ECE 34 Jose Schutt Aine 6
27 CMOS Inverter VTC Derivation Assume that transistors are matched Vertical segment of VTC is when both Q N and Q P are saturated No channel length modulation effect = 0 Vertical segment occurs at v i =V DD / V IL : maximum permitted logic0 level of input (slope=1) V IH : minimum permitted logic1 level of input (slope=1) To determine V IH, assume Q N in triode region and Q P in saturation region 1 1 v V v v V v V I t o o DD I t Next, we differentiate both sides relative to v i dv dv v V v v V v V o o I t o o DD I t dvi dvi ECE 34 Jose Schutt Aine 7
28 CMOS Inverter VTC Substitute v i =V IH and dv o /dv i = 1 v o V IH After substitutions, we get V DD 1 V 5 V V 8 IH DD t Same analysis can be repeated for V IL to get 1 V 3 V V 8 IL DD t ECE 34 Jose Schutt Aine 8
29 CMOS Inverter Noise Margins 1 V 5 V V 8 IH DD t 1 V 3 V V 8 IL DD t 1 NM 3 V V 8 H DD t 1 NM 3 V V 8 L DD t Symmetry in VTC equal noise margins ECE 34 Jose Schutt Aine 9
30 Matched CMOS Inverter VTC CMOS inverter can be made to switch at specific threshold voltage by appropriately sizing the transistors W n W L L p p Symmetrical transfer characteristics is obtained via matching equal current driving capabilities in both directions (pullup and pulldown) n ECE 34 Jose Schutt Aine 30
31 VTC and Noise Margins  Problem An inverter is designed with equalsized NMOS and PMOS transistors and fabricated in a 0.8micron CMOS technology for which k n = 10 A/V, k p = 60 A/V, V tn = V tp =0.7 V, V DD = 3V, L n =L p = 0.8 m, W n = W p = 1. m, find V IL, V IH and the noise margins. Equal sizes NMOS and PMOS, but k n =k p V t = 0.7V For V IH : Q N in triode and Q P in saturation W 1 1 W k V V V V k V V V ' ' n I t o o p DD I t L n L p ECE 34 Jose Schutt Aine 31
32 VTC and Noise Margins Problem (cont ) 4 V V V V V V V I t o o DD I t (1) Differentiating both sides relative to V I results in: V :4 o Vo V 4 4 I Vt Vo Vo VDD VI Vt ( 1) V V V I I I Substitute the values together with: V I V IH Vo and 1 V I ECE 34 Jose Schutt Aine 3
33 VTC and Noise Margins Problem (cont ) 4 V V 4V V IH o o IH V IH 8V o Vo () From (1) : V V V V IH o o IH V V V V IH o o IH (3) solving () & (3) : 1.55Vo 4.97Vo V 0.V VIH 1.5V o ECE 34 Jose Schutt Aine 33
34 VTC and Noise Margins Problem (cont ) For V IL : Q N is in saturation and Q P in triode 1 W W 1 k V V k V V V V V V V ' ' n I t p DD I t DD o DD o L n L p 1 V V V 3 V I I o o 1 V V 3 V 3 V I I o o (1) V o V VI VI 3 Vo 3 Vo V V V I I I o ECE 34 Jose Schutt Aine 34
35 V I V IL Vo and 1 V I V 1.4.3V 3V 3V V VTC and Noise Margins Problem (cont ) IL IL IL o o V 3 o From (1) : V V 3 V 3 V V V 3 V 3 V IL IL o o o o o o ECE 34 Jose Schutt Aine 35
36 VTC and Noise Margins Problem (cont ) Vo.96V V 0.81V IL Noise Margins: NM NM H L V V Since Q N and Q P are not matched, the VTC is not symmetric ECE 34 Jose Schutt Aine 36
37 CMOS Dynamic Operation Exact analysis is too tedious Replace all the capacitances in the circuit by a single equivalent capacitance C connected between the output node of the inverter and ground Analyze capacitively loaded inverter to determine propagation delay ECE 34 Jose Schutt Aine 37
38 CMOS Dynamic Operation C C C C C C C C gd1 gd db1 db g3 g4 w ECE 34 Jose Schutt Aine 38
39 CMOS Dynamic Operation ECE 34 Jose Schutt Aine 39
40 CMOS Dynamic Operation Need interval t PHL during which v o reduces from V DD to V DD / I t CV V av PHL DD DD / Which gives I av is given by t PHL CV I DD av 1 Iav idn E idn M ECE 34 Jose Schutt Aine 40
41 CMOS Dynamic Operation where 1 W i E k V V L ' DN n DD tn n and ' W V 1 DD VDD idn M kn VDD Vtn L n this gives t PHL nc k W / L V ' n n DD ECE 34 Jose Schutt Aine 41
42 Where a is given by CMOS Dynamic Operation n 7 4 3V V tn DD V V tn DD Likewise, t PLH is given by t PLH C 7 4 VDD V DD p with p ' k / p W L V 3 Vtp Vtp p DD ECE 34 Jose Schutt Aine 4
43 Where a is given by CMOS Dynamic Operation 1 t t t P PHL PLH Components can be equalized by matching transistors t P is proportional to C reduce capacitance Larger V DD means lower t p Conflicting requirements exist ECE 34 Jose Schutt Aine 43
44 CMOS Propagation Delay ECE 34 Jose Schutt Aine 44
45 CMOS Propagation Delay Capacitance C is the sum of: Internal capacitances of Q N and Q P Interconnect wire capacitance Input of the other logic gate t PHL 1.6C k W / L V ' n n DD To lower propagation delay Minimize C Increase process transconductance k Increase W/L Increase V DD ECE 34 Jose Schutt Aine 45
46 CMOS Inverter Problem A CMOS inverter for which k n =10 k p =100 A/V and V t =0.5 V is connected as shown to a sinusoidal signal source having a Thevenin equivalent voltage of 0.1V peak amplitude and resistance of 100 k. What signal voltage appears at node A with v I = +1.5 V and v I = 1.5 V? ECE 34 Jose Schutt Aine 46
47 CMOS Inverter Problem (cont ) For v I = 1.5 V, the NMOS operates in the triode region while the PMOS is off. r DSn k k v V n I t va mv ECE 34 Jose Schutt Aine 47
48 CMOS Inverter Problem (cont ) For v I = 1.5 V, the PMOS operates with r DSP kp vi Vt va mv 10 ECE 34 Jose Schutt Aine 48
49 n Propagation Delay  Example Find the propagation delay for a minimumsize inverter for which k n =3k p =180 A/V and (W/L) n = (W/L) p =0.75 m/0.5 m, V DD = 3.3 V, V tn = V tp = 0.7 V, and the capacitance is roughly ff/mm of device width plus 1 ff/device. What does t p become if the design is changed to a matched one? Use the method of average current Solution 7 3V tn V tn VDD VDD nc ff ff tphl ' k / n W L V n DD ECE 34 Jose Schutt Aine 49
50 Propagation Delay  Example tphl 4.85 ps Since V V, then 1.73 tn tp n p W W We also have, hence L n L p ' kn tplh tphl ps ' k n 1 1 t P tphl tplh 9.7 ps ECE 34 Jose Schutt Aine 50
51 Propagation Delay  Example If both devices are matched, then k ' p k ' n t PLH t PHL and 1 t p tphl tplh tphl 4.85 ps ECE 34 Jose Schutt Aine 51
52 CMOS Dynamic Power Dissipation In every cycle Q N dissipate ½ CV DD of energy Q P dissipate ½ CV DD of energy Total energy dissipation is CV DD If inverter is switched at f cycles per second, dynamic power dissipation is: P D fcv DD ECE 34 Jose Schutt Aine 5
53 Power Dissipation  Example In this problem, we estimate the inverter power dissipation resulting from the current pulse that flows in Q N and Q P when the input pulse has finite rise and fall times. Let V tn =V tp =0.5 V, V DD = 1.8V, and k n =k p =450A/V. Let the input rising and falling edges be linear ramps with the 0toV DD and V DD to0 transitions taking 1 ns each. Find I peak ECE 34 Jose Schutt Aine 53
54 Power Dissipation  Example To determine the energy drawn from the supply per transition, assume that the current pulse can be approximated by a triangle with a base corresponding to the time for the rising or falling edge to go from V t to V DD V t, and the height equal to I peak. Also, determine the power dissipation that results when the inverter is switched at 100 MHz. ECE 34 Jose Schutt Aine 54
55 Power Dissipation  Example 1 W VDD IPeak ncox Vtn L n I Peak 1 A A V ECE 34 Jose Schutt Aine 55
56 Power Dissipation  Example The time when the input reaches V t is: 0.5 1ns 0.8ns 1.8 The time when the input reaches V DD  V t is: ns 0.7ns 1.8 The base of the triangle is t ns wide ECE 34 Jose Schutt Aine 56
57 Power Dissipation  Example 1 1 E IPeak VDD t 36 A ns E 14.3 femtojoules 6 15 P f E W ECE 34 Jose Schutt Aine 57
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