Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model


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1 Content MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni Digital Switching 1
2 Content MOS Devices and Switching Circuits (Majority Carrier Devices) MOS SWITCHING CIRCUITS nmos Logic (Ratioed Logic) CMOS Logic Switching Times of CMOS Inverter CMOS Power Dissipation A Cantoni Digital Switching 2
3 Device Switching Bipolar (Minority Carrier Devices) Review of Charge Control Model Saturated Inverter Switching Saturation Control Transistor Transistor Logic (TTL) Basics A Cantoni Digital Switching 3
4 MetalInsulatorSemiconductor(MIS) metal insulator semiconductor ohmic contact V 4
5 Idealised MIS Vacuum Level E C Flat Band Model φ m φ n E f E Fermi Level E E C f E i E V E V Metal Insulator Semiconductor
6 Excess Local Charge n type p type POSITIVE mobile Increased concentration of mobile holes  E V bent closer to E F >inversion. Reduced concentration of mobile electronse C bentawayfrome F. Leaves positively ionised donors. > space charge. Increased concentration of mobile holes  E V bent closer to E F >accumulation. Reduced concentration of mobile electronse C bentawayfrome F Increased concentration of mobile Increased concentration of mobile NEGATIVE mobile electronse C bentclosertoe F > accumulation Reduced concentration of mobile holesbye V bentawayfrome F electronse C bentclosertoe F >inversion Reduced concentration of mobile holes E V bentawayfrome F. Leaves negatively ionised acceptors > space charge
7 Idealised MISExternal Bias ev E f E C E f E i E V ξ n Charge on metal V Metal Insulator V Semiconductor Mobile Electrons ρ( x) x Accumulation
8 Idealised MIS Negative Bias on Metal Depletion Charge on metal E f ev   E C E E f i E V ξ p V Metal Insulator Semiconductor Surface Ionised Donors V ρ( x) x 8
9 Idealised MIS Negative Bias on Metal Inversion Charge on metal E f ev E C E E f i E V ξ p V Metal Insulator Semiconductor Surface Mobile Holes and Ionised Donors V ρ( x) x 9
10 MOS Transistor n + Oxide n + P Substrate BULK n + SOURCE GATE n + DRAIN W L Intel L ~ 45 nm (45 X 109 m) 10
11 MOS Transistor Symbols D D D G B G G N Channel S S S D D D G B G G P Channel S S S 11
12 MOSFET Region of Operation I DS Pinch Off Determine Region of Operation Check V = V V GS G S V GSN More positive relative to V T V DS Check V = V V GD G D relative to V T 12
13 V > MOSFET n channel Enhancement Devices 0 Cut Off: TN VGSN < VTN VDSN 0 IDN = 0 I DSN and V GSN More positive Ohmic/Triode Region: VGSN > VTN VGDN > VTN VDSN < VGSN VTN 1 I = k V V V V 2 ( ) 2 DN N GSN TN DSN DSN V DSN Saturation: VGSN > VTN VGDN < VTN 0 V V V GSN TN DSN V V V 0 DSN GSN TN kn IDN = ( VGSN VTN)
14 MOS Inverters VDD VDD VDD VDD VDD RD Pull Up D Pu Pu Pu Pull Down G B Pd Pd Pd S QPD Resistor requires large area and gives RC transient responses V OH <V DD V TN H noise margin low Dissipates power when output Low No power dissipation when output High nmos A Cantoni 2008 Digital Switching Good size Compromise between noise margin and speed Dissipates power when output Low No power dissipation when output High CMOS Controlled pull up and pull down. Eliminates the compromise between speed and noise margin Has no power dissipation in steady state H and L 14
15 CMOS Inverter V I G G i DP i DN VCC S D D S T P v o T N V I V O V CC n + n + p + p + p well nsubstrate 15
16 CMOS Inverter Consider initially the case of perfectly matched complementary ideal p and n devicesinthecmosinverter& V CC >2V T V o STATIC CHARACTERISTIC T N OFF A T N SATURATED T P OHMIC W n Ln VTN = VTP = VT k = kn = k P = W p L V CC p u u e h D' V O = V i G S D T N SATURATED T P SATURATED T N OHMIC T P SATURATED v i i DP i DN G D D T P T N v o T P OFF S V DD BA Cantoni 2008Digital Switching V i 16
17 Unbuffered CMOS GATES The generic structure for unbuffered CMOS logic V CC Input vector (x, y, z, C) pnet N P nnet N N pchannel transistors Output f nchannel transistors Transmission function T P Transmission function T N T T P N = 1 Output = 1 = = 0 ( V ) CC T T P N = 0 = 0 not allowed: floating output. T T P N = 0 Output = 0 = = 1 ( GND) T T P N = 1 = 1 notallowed,currentfrom V DD toground. Complementary No Steady Current and Valid Output 17
18 Unbuffered CMOS GATES x V DD z y f f( x, y, z) ( ) ( ) T = f( x, y, z,..) = x+ y z= x y z = x y+ z N = x+ y z x y T (,,,..) z P = f x y z = x+ yz Network characteristics: n and p channel always paired Note the negated variables! 18
19 Buffered CMOS input vector (x, y, z, C) pnet N P nnet N N G G S D D V DD G G S D D S S 19
20 MOSFET Capacitances Operating Region C GB C GS C GD C OLS C OLD Cutoff X 0 0 X X Triode 0 X X X X Saturated 0 X 0 X X C Source Gate Drain OLS C GS C GD C OLD C SB CGB CDB Total gate capacitance C = C + C + C + C + C G GS GD GB OLS OLD 20
21 Inverter Switching Identify Region of Operation Identify Initial Conditions Assume a Region of Operation {cutoff, forward active, saturated} Identify Final Conditions Assuming Region of Operation Persist for all time Simplify equations Find Solution Consistent Circuit Solution Y N Use solution to Determine Time when New Region of Operation is entered or Final State reached 21
22 CMOS Switching G S V CC V V V, 0p t τ o CC T 1 V CC 0V t = 0 v i i DP i DN G D D S T P T N I O C v o The n channel FET is in the saturated region and the p channel is OFF V p V V, τ < t o CC T 1 The n channel FET is in the ohmic region and the p channel is OFF. 22
23 CMOS Switching V i V CC t V CC N Saturated V CC V T N Ohmic ID t=0 C V V V o CC T τ 1 ID V CC V pv V o CC T C 1 ( ) 2 ID = k VCC VT 2 1 I = k ( V V ) V V 2 2 D CC T o o 23
24 Power Dissipation V o V o T N OFF A T N SATURATED T P OHMIC D' T N SATURATED T P SATURATED D T N OHMIC T P SATURATED T P OFF V CC I D V T V ( V V ) CC 2 CC T 24
25 Power Dissipation V CC V V I T V T tr tf I PK P = V I AV SW CC AV SW = V I t f CC PK sw tsw = tr = tf 25
26 Power Dissipation Dynamic Power Consumption Charging and Discharging Capacitors 2 PC = CLV f Leaking currents through diodes and transistors P = V I S CC CC CC Total Power P = V I t f + C V f + V I 2 T CC PK sw L CC CC CC P C C V f V I 2 T = ( PD + L) CC + CC CC 26
27 Static BJT Device Modelling E B C COLLECTOR p+ isolation n+ p + p nepitaxy n + p + BASE EMITTER n+ buried layer NPN psubstrate (c) NPN Schematic Symbol (a) NPN Crosssectional view. B E n+ p n C (b) NPN Idealized transistor structure.
28 BJT Region of Operation Determine Region of Operation Check relative to V = V V BE B E V Juntction_ ON Check relative to V = V V BC B C V Juntction _ ON 28
29 BJT Regions of Operation I C ma 6 Saturated IB = 0.05mA 5 IB = 0.04mA 4 IB = 0.03mA 3 2 Forward Active I B = 0.02mA 10 1 IB = 0.01mA I B = 0 IB = 0.01mA V CE Reverse Active 0.04 CutOff BV CEO
30 Charge Control Model (npn BJT) i i i C B E q F i B B qf τ F C BC τf τbf qf _ + + _ dq BC C i C _ q R + dt dq F + dt E i E _ dq R dt dq BE dt C BE qr + τ R τ qr τ R 1 1 qf dq BC 1 1 = qr + τf dt τr τbr qf dqf dqbe dqbc qr dqr = τ dt dt dt τ dt BF 1 1 dqf dqbe qr = qf + + τf τbf dt dt τr BR BR dq dt R Minority Carrier Injection BE Space Charge Minority Carrier Injection BC 30
31 BJT Inverter Switching Identify Region of Operation Identify Initial Conditions Assume a Region of Operation {cutoff, forward active, saturated} Identify Final Conditions Assuming Region of Operation Persist for all time Simplify equations Find Solution Consistent Circuit Solution Y N Use solution to Determine Time when New Region of Operation is entered or Final State reached 31
32 BJT Inverter Switching v i V2  V1 i ( ) C t t 1 t t 2 3 t 2 ib( t) Charge Storage Delay t S v BE( t ) t 2 CO CO FA SAT SAT FA CO 32
33 BJT Inverter Switching Forward Active Region V CC C i C qf τ i B F C BC _ + dqbc dt + V 2 q F τf τbf qf + _ dq F dt + _ dq BE dt C BE Circuit simplification by appropriate approximations 33
34 BJT Inverter Switching Forward Active Region V 2 v( t) i V CC R C i C V 1 v ( ) be t V 2 v i + R i i B V CE V 1 V 1 V CC VCE SAT βfib ON 0 t 1 ( t + t ) 2 1 v ( ) ce t VCC β I R F B ON C IC SAT i c (t) 34
35 Simulation of Clamp MBD101 1K 3V 1K 3V + v i 5K i B i D i C BC337 + v i 5K i B i C BC337 35
36 Schottky Transistor V CC V CC R C i Rc R C i Rc I (ON) i D i C I (ON) i C i B The diode limits v BC to 0.4 V maximum q R is negligible and the transistor is in the active region. Downside: V CE(SAT) = V BE(ON)  V D(ON) 0.3 to 0.4 V higher low level and hence lower margin. 36
37 Bipolar Logic TTL TransistorTransistor Logic (TTL) developed from earlier bipolar logic such as Resistor Transistor logic (RTL) and DiodeTransistor Logic(DTL). V CC (5V) R 2 (1.6K) R c (130) R 1 (4K) Q 3 Q 2 Q 1 R 3 (1K) Q 4 A Standard TTL Inverter 37
38 E TTL Input Diode Model B C TRANSISTOR There is a big difference between using two diodes and the transistor! V CC (5V) R 1 (4K) R 2 (1.6K) Q 2 Q 3 R c (130) R 3 (1K) Q 4 VI > VD + VBE 2VBE Vo LOW VI < VD + VBE 2VBE Vo HIGH 38
39 TTL The big difference between the equivalent diodecircuit and the transistor inputcircuit is the transistor base to collector current gain action when the input (emitter) is connected low R 1 (4K) R 2 (1.6K) R c (130) Q 3 V CC (5V) Q 4 will turn off rapidly due to the increase initscollectorcurrentasq 3 turnson. 3 Q 2 i B V CC V R I BE Q 1 R 3 (1K) Q 4 The 130 Ohm collector resistor on Q 3 limits the current glitch that flows from supply to ground i = βi i < 0 C B BQ2 Q1 in Forward Active! V 2V CE BE_ ON 39
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