Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model


 Elfrieda Montgomery
 4 years ago
 Views:
Transcription
1 Content MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni Digital Switching 1
2 Content MOS Devices and Switching Circuits (Majority Carrier Devices) MOS SWITCHING CIRCUITS nmos Logic (Ratioed Logic) CMOS Logic Switching Times of CMOS Inverter CMOS Power Dissipation A Cantoni Digital Switching 2
3 Device Switching Bipolar (Minority Carrier Devices) Review of Charge Control Model Saturated Inverter Switching Saturation Control Transistor Transistor Logic (TTL) Basics A Cantoni Digital Switching 3
4 MetalInsulatorSemiconductor(MIS) metal insulator semiconductor ohmic contact V 4
5 Idealised MIS Vacuum Level E C Flat Band Model φ m φ n E f E Fermi Level E E C f E i E V E V Metal Insulator Semiconductor
6 Excess Local Charge n type p type POSITIVE mobile Increased concentration of mobile holes  E V bent closer to E F >inversion. Reduced concentration of mobile electronse C bentawayfrome F. Leaves positively ionised donors. > space charge. Increased concentration of mobile holes  E V bent closer to E F >accumulation. Reduced concentration of mobile electronse C bentawayfrome F Increased concentration of mobile Increased concentration of mobile NEGATIVE mobile electronse C bentclosertoe F > accumulation Reduced concentration of mobile holesbye V bentawayfrome F electronse C bentclosertoe F >inversion Reduced concentration of mobile holes E V bentawayfrome F. Leaves negatively ionised acceptors > space charge
7 Idealised MISExternal Bias ev E f E C E f E i E V ξ n Charge on metal V Metal Insulator V Semiconductor Mobile Electrons ρ( x) x Accumulation
8 Idealised MIS Negative Bias on Metal Depletion Charge on metal E f ev   E C E E f i E V ξ p V Metal Insulator Semiconductor Surface Ionised Donors V ρ( x) x 8
9 Idealised MIS Negative Bias on Metal Inversion Charge on metal E f ev E C E E f i E V ξ p V Metal Insulator Semiconductor Surface Mobile Holes and Ionised Donors V ρ( x) x 9
10 MOS Transistor n + Oxide n + P Substrate BULK n + SOURCE GATE n + DRAIN W L Intel L ~ 45 nm (45 X 109 m) 10
11 MOS Transistor Symbols D D D G B G G N Channel S S S D D D G B G G P Channel S S S 11
12 MOSFET Region of Operation I DS Pinch Off Determine Region of Operation Check V = V V GS G S V GSN More positive relative to V T V DS Check V = V V GD G D relative to V T 12
13 V > MOSFET n channel Enhancement Devices 0 Cut Off: TN VGSN < VTN VDSN 0 IDN = 0 I DSN and V GSN More positive Ohmic/Triode Region: VGSN > VTN VGDN > VTN VDSN < VGSN VTN 1 I = k V V V V 2 ( ) 2 DN N GSN TN DSN DSN V DSN Saturation: VGSN > VTN VGDN < VTN 0 V V V GSN TN DSN V V V 0 DSN GSN TN kn IDN = ( VGSN VTN)
14 MOS Inverters VDD VDD VDD VDD VDD RD Pull Up D Pu Pu Pu Pull Down G B Pd Pd Pd S QPD Resistor requires large area and gives RC transient responses V OH <V DD V TN H noise margin low Dissipates power when output Low No power dissipation when output High nmos A Cantoni 2008 Digital Switching Good size Compromise between noise margin and speed Dissipates power when output Low No power dissipation when output High CMOS Controlled pull up and pull down. Eliminates the compromise between speed and noise margin Has no power dissipation in steady state H and L 14
15 CMOS Inverter V I G G i DP i DN VCC S D D S T P v o T N V I V O V CC n + n + p + p + p well nsubstrate 15
16 CMOS Inverter Consider initially the case of perfectly matched complementary ideal p and n devicesinthecmosinverter& V CC >2V T V o STATIC CHARACTERISTIC T N OFF A T N SATURATED T P OHMIC W n Ln VTN = VTP = VT k = kn = k P = W p L V CC p u u e h D' V O = V i G S D T N SATURATED T P SATURATED T N OHMIC T P SATURATED v i i DP i DN G D D T P T N v o T P OFF S V DD BA Cantoni 2008Digital Switching V i 16
17 Unbuffered CMOS GATES The generic structure for unbuffered CMOS logic V CC Input vector (x, y, z, C) pnet N P nnet N N pchannel transistors Output f nchannel transistors Transmission function T P Transmission function T N T T P N = 1 Output = 1 = = 0 ( V ) CC T T P N = 0 = 0 not allowed: floating output. T T P N = 0 Output = 0 = = 1 ( GND) T T P N = 1 = 1 notallowed,currentfrom V DD toground. Complementary No Steady Current and Valid Output 17
18 Unbuffered CMOS GATES x V DD z y f f( x, y, z) ( ) ( ) T = f( x, y, z,..) = x+ y z= x y z = x y+ z N = x+ y z x y T (,,,..) z P = f x y z = x+ yz Network characteristics: n and p channel always paired Note the negated variables! 18
19 Buffered CMOS input vector (x, y, z, C) pnet N P nnet N N G G S D D V DD G G S D D S S 19
20 MOSFET Capacitances Operating Region C GB C GS C GD C OLS C OLD Cutoff X 0 0 X X Triode 0 X X X X Saturated 0 X 0 X X C Source Gate Drain OLS C GS C GD C OLD C SB CGB CDB Total gate capacitance C = C + C + C + C + C G GS GD GB OLS OLD 20
21 Inverter Switching Identify Region of Operation Identify Initial Conditions Assume a Region of Operation {cutoff, forward active, saturated} Identify Final Conditions Assuming Region of Operation Persist for all time Simplify equations Find Solution Consistent Circuit Solution Y N Use solution to Determine Time when New Region of Operation is entered or Final State reached 21
22 CMOS Switching G S V CC V V V, 0p t τ o CC T 1 V CC 0V t = 0 v i i DP i DN G D D S T P T N I O C v o The n channel FET is in the saturated region and the p channel is OFF V p V V, τ < t o CC T 1 The n channel FET is in the ohmic region and the p channel is OFF. 22
23 CMOS Switching V i V CC t V CC N Saturated V CC V T N Ohmic ID t=0 C V V V o CC T τ 1 ID V CC V pv V o CC T C 1 ( ) 2 ID = k VCC VT 2 1 I = k ( V V ) V V 2 2 D CC T o o 23
24 Power Dissipation V o V o T N OFF A T N SATURATED T P OHMIC D' T N SATURATED T P SATURATED D T N OHMIC T P SATURATED T P OFF V CC I D V T V ( V V ) CC 2 CC T 24
25 Power Dissipation V CC V V I T V T tr tf I PK P = V I AV SW CC AV SW = V I t f CC PK sw tsw = tr = tf 25
26 Power Dissipation Dynamic Power Consumption Charging and Discharging Capacitors 2 PC = CLV f Leaking currents through diodes and transistors P = V I S CC CC CC Total Power P = V I t f + C V f + V I 2 T CC PK sw L CC CC CC P C C V f V I 2 T = ( PD + L) CC + CC CC 26
27 Static BJT Device Modelling E B C COLLECTOR p+ isolation n+ p + p nepitaxy n + p + BASE EMITTER n+ buried layer NPN psubstrate (c) NPN Schematic Symbol (a) NPN Crosssectional view. B E n+ p n C (b) NPN Idealized transistor structure.
28 BJT Region of Operation Determine Region of Operation Check relative to V = V V BE B E V Juntction_ ON Check relative to V = V V BC B C V Juntction _ ON 28
29 BJT Regions of Operation I C ma 6 Saturated IB = 0.05mA 5 IB = 0.04mA 4 IB = 0.03mA 3 2 Forward Active I B = 0.02mA 10 1 IB = 0.01mA I B = 0 IB = 0.01mA V CE Reverse Active 0.04 CutOff BV CEO
30 Charge Control Model (npn BJT) i i i C B E q F i B B qf τ F C BC τf τbf qf _ + + _ dq BC C i C _ q R + dt dq F + dt E i E _ dq R dt dq BE dt C BE qr + τ R τ qr τ R 1 1 qf dq BC 1 1 = qr + τf dt τr τbr qf dqf dqbe dqbc qr dqr = τ dt dt dt τ dt BF 1 1 dqf dqbe qr = qf + + τf τbf dt dt τr BR BR dq dt R Minority Carrier Injection BE Space Charge Minority Carrier Injection BC 30
31 BJT Inverter Switching Identify Region of Operation Identify Initial Conditions Assume a Region of Operation {cutoff, forward active, saturated} Identify Final Conditions Assuming Region of Operation Persist for all time Simplify equations Find Solution Consistent Circuit Solution Y N Use solution to Determine Time when New Region of Operation is entered or Final State reached 31
32 BJT Inverter Switching v i V2  V1 i ( ) C t t 1 t t 2 3 t 2 ib( t) Charge Storage Delay t S v BE( t ) t 2 CO CO FA SAT SAT FA CO 32
33 BJT Inverter Switching Forward Active Region V CC C i C qf τ i B F C BC _ + dqbc dt + V 2 q F τf τbf qf + _ dq F dt + _ dq BE dt C BE Circuit simplification by appropriate approximations 33
34 BJT Inverter Switching Forward Active Region V 2 v( t) i V CC R C i C V 1 v ( ) be t V 2 v i + R i i B V CE V 1 V 1 V CC VCE SAT βfib ON 0 t 1 ( t + t ) 2 1 v ( ) ce t VCC β I R F B ON C IC SAT i c (t) 34
35 Simulation of Clamp MBD101 1K 3V 1K 3V + v i 5K i B i D i C BC337 + v i 5K i B i C BC337 35
36 Schottky Transistor V CC V CC R C i Rc R C i Rc I (ON) i D i C I (ON) i C i B The diode limits v BC to 0.4 V maximum q R is negligible and the transistor is in the active region. Downside: V CE(SAT) = V BE(ON)  V D(ON) 0.3 to 0.4 V higher low level and hence lower margin. 36
37 Bipolar Logic TTL TransistorTransistor Logic (TTL) developed from earlier bipolar logic such as Resistor Transistor logic (RTL) and DiodeTransistor Logic(DTL). V CC (5V) R 2 (1.6K) R c (130) R 1 (4K) Q 3 Q 2 Q 1 R 3 (1K) Q 4 A Standard TTL Inverter 37
38 E TTL Input Diode Model B C TRANSISTOR There is a big difference between using two diodes and the transistor! V CC (5V) R 1 (4K) R 2 (1.6K) Q 2 Q 3 R c (130) R 3 (1K) Q 4 VI > VD + VBE 2VBE Vo LOW VI < VD + VBE 2VBE Vo HIGH 38
39 TTL The big difference between the equivalent diodecircuit and the transistor inputcircuit is the transistor base to collector current gain action when the input (emitter) is connected low R 1 (4K) R 2 (1.6K) R c (130) Q 3 V CC (5V) Q 4 will turn off rapidly due to the increase initscollectorcurrentasq 3 turnson. 3 Q 2 i B V CC V R I BE Q 1 R 3 (1K) Q 4 The 130 Ohm collector resistor on Q 3 limits the current glitch that flows from supply to ground i = βi i < 0 C B BQ2 Q1 in Forward Active! V 2V CE BE_ ON 39
The Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationEE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: nchannel MOSFET Source Gate L Drain W L EFF Poly Gate oxide nactive psub depletion region (electrically
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationMOS SWITCHING CIRCUITS
ontent MOS SWIHING IRUIS nmos Inverter nmos Logic Functions MOS Inverter UNBUFFR MOS LOGI BUFFR MOS LOGI A antoni 010igital Switching 1 MOS Inverters V V V V V R Pull Up Pu Pu Pu Pull own G B Pd Pd Pd
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationFundamentals of the Metal Oxide Semiconductor FieldEffect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor FieldEffect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX =  4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationContent. MIS Capacitor. Accumulation Depletion Inversion MOS CAPACITOR. A Cantoni Digital Switching
Content MIS Capacitor Accumulation Depletion Inversion MOS CAPACITOR 1 MIS Capacitor Metal Oxide C ox psi C s Components of a capacitance model for the MIS structure 2 MIS Capacitor Accumulation ρ( x)
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationChapter 13 SmallSignal Modeling and Linear Amplification
Chapter 13 SmallSignal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 131 Chapter Goals Understanding of concepts related to: Transistors
More informationECE 497 JS Lecture  12 Device Technologies
ECE 497 JS Lecture  12 Device Technologies Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationDigital Electronics Part II  Circuits
Digital Electronics Part  Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are nonlinear, consequently we will introduce a graphical technique for analysing such circuits The
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Threeterminal device whose voltagecurrent relationship is controlled by a third voltage
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationMicroelectronic Devices and Circuits Lecture 9  MOS Capacitors I  Outline Announcements Problem set 5 
6.012  Microelectronic Devices and Circuits Lecture 9  MOS Capacitors I  Outline Announcements Problem set 5  Posted on Stellar. Due net Wednesday. Qualitative description  MOS in thermal equilibrium
More informationChapter 2 CMOS Transistor Theory. JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor JinFu Li, EE,
More informationFIELDEFFECT TRANSISTORS
FIELEFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancementtype NMOS transistor 3 IV characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationCHAPTER 5 MOS FIELDEFFECT TRANSISTORS
CHAPTER 5 MOS FIELDEFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancementtype NMOS transistor 5.3 IV characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5
More informationDigital Electronics Part II Electronics, Devices and Circuits
Digital Electronics Part Electronics, Devices and Circuits Dr.. J. Wassell ntroduction n the coming lectures we will consider how logic gates can be built using electronic circuits First, basic concepts
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationLecture 13  Digital Circuits (II) MOS Inverter Circuits. March 20, 2003
6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS
More informationGEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationMetaloxidesemiconductor field effect transistors (2 lectures)
Metalidesemiconductor field effect transistors ( lectures) MOS physics (brief in book) Currentvoltage characteristics  pinchoff / channel length modulation  weak inversion  velocity saturation 
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and crosssectional area 100µm 2
More informationDigital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (3611301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
More informationElectronic Devices and Circuits Lecture 15  Digital Circuits: Inverter Basics  Outline Announcements. = total current; I D
6.012  Electronic Devices and Circuits Lecture 15  Digital Circuits: Inverter asics  Outline Announcements Handout  Lecture Outline and Summary The MOSFET alpha factor  use definition in lecture,
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationP. R. Nelson 1 ECE418  VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418  VLSI Midterm Exam Solutions 1. (8 points) Draw the crosssection view for AA. The crosssection view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationSwitching circuits: basics and switching speed
ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More informationLecture 19  pn Junction (cont.) October 18, Ideal pn junction out of equilibrium (cont.) 2. pn junction diode: parasitics, dynamics
6.720J/3.43J  Integrated Microelectronic Devices  Fall 2002 Lecture 191 Lecture 19  pn Junction (cont.) October 18, 2002 Contents: 1. Ideal pn junction out of equilibrium (cont.) 2. pn junction diode:
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationEE105  Fall 2005 Microelectronic Devices and Circuits
EE105  Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationHomework Assignment 09
Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationCMOS Logic Gates. University of Connecticut 181
CMOS Logic Gates University of Connecticut 181 Basic CMOS Inverter Operation V IN P O N O pchannel enhancementtype MOSFET; V T < 0 nchannel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationAppendix 1: List of symbols
Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More information3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an nchannel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC baseemitter voltage (note: normally plot vs. base current, so we must return to EbersMoll): I C I S e V BE V th I S e V th
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ FieldOxyde (SiO 2 ) psubstrate p+ stopper Bulk Contact CROSSSECTION of NMOS Transistor CrossSection of CMOS Technology MOS transistors
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationChargeStorage Elements: BaseCharging Capacitance C b
ChargeStorage Elements: BaseCharging Capacitance C b * Minority electrons are stored in the base  this charge q NB is a function of the baseemitter voltage * base is still neutral... majority carriers
More informationCapacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009
Wilfrid Laurier University June 4, 2009 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists of two conductive
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationBipolar Junction Transistor (BJT)  Introduction
Bipolar Junction Transistor (BJT)  Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More information