CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.


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1 CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University of labama in Huntsville = R n = leksandar Milenkovic ( ) V in = V in = 9/8/4 VLSI esign I;. Milenkovic 4 Course dministration Instructor: T: Labs: URL: Text: leksandar Milenkovic E 7L Office Hrs: MW 9:: athima Tareen ccounts on Solaris machines, Lab# is on nalysis and esign of igital ICs, 3 rd Edition Hodges et. al., 4 Previous: IC abrication (slides, Chapter 3) Today: MOS Transistors (slides, Chapter ) CMOS Properties ull railtorail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless lways a path to V dd or in steady state low output impedance (output resistance in kω range) large fanout (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steadystate input current No direct path steadystate between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors 9/8/4 VLSI esign I;. Milenkovic 9/8/4 VLSI esign I;. Milenkovic 5 V in CMOS Inverter: irst Look Review: Short Channel IV Plot (NMOS) I ().5 X 4 V GS =.5V V GS =.V.5 V GS =.5V.5 V GS =.V Linear dependence V S (V) NMOS transistor,.5um, L d =.5um, W/L =.5, =.5V, V T =.4V 9/8/4 VLSI esign I;. Milenkovic 3 9/8/4 VLSI esign I;. Milenkovic 6
2 Short Channel IV Plot (PMOS) ll polarities of all voltages and currents are reversed  V S (V)  V GS = .V V GS = .5V V GS = .V V GS = .5V  X 4 PMOS transistor,.5um, L d =.5um, W/L =.5, =.5V, V T = .4V 9/8/4 VLSI esign I;. Milenkovic I () CMOS Inverter VTC /8/4 VLSI esign I;. Milenkovic Transforming PMOS IV Lines CMOS Inverter VTC Want common coordinate set V in,, and I n I Sp = I Sn V GSn = V in ; V GSp = V in  V Sn = ; V Sp =  I n NMOS off PMOS res.5 NMOS sat PMOS res V GSp =  V GSp = .5 V in = V in =.5 Mirror around xaxis V in = + V GSp I n = I p Horiz. shift over = + V Sp Vout V in = V in =.5.5 NMOS sat PMOS sat.5 NMOS res PMOS sat NMOS res PMOS off /8/4 VLSI esign I;. Milenkovic 8 9/8/4 VLSI esign I;. Milenkovic PMOS.5 V in = V X 4 CMOS Inverter Load Lines NMOS V in =.5V CMOS Inverter: Switch Model of ynamic ehavior V in =.5V.5 V in =.V R p I n () V in =.V V in =.5V V V in =.5V in = V V in = V V in =.5V.5 V in =.5V V in =.V V in =.V V in =.5V V in =.5V V in = V.5um, W/L n =.5, W/L p = 4.5, =.5V, V Tn =.4V, V Tp = .4V 9/8/4 VLSI esign I;. Milenkovic 9 C L R n V V in = in = 9/8/4 VLSI esign I;. Milenkovic
3 CMOS Inverter: Switch Model of ynamic ehavior Switch Threshold Example In our generic.5 micron CMOS process, using the process parameters from slide L3.5, a =.5V, and a minimum size NMOS device ((W/L) n of.5) R p R n NMOS PMOS V T (V) γ(v.5 ) V ST (V).63  k (/V ) 5 x 63 x 6 λ(v  ).6 . V in = V in = Gate response time is determined by the time to charge through R p (discharge through R n ) 9/8/4 VLSI esign I;. Milenkovic 3 (W/L) p (W/L) n = 9/8/4 VLSI esign I;. Milenkovic 6 Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics Switch Threshold Example In our generic.5 micron CMOS process, using the process parameters, a =.5V, and a minimum size NMOS device ((W/L) n of.5) NMOS PMOS V T (V) γ(v.5 ) V ST (V).63  k (/V ) 5 x 63 x 6 λ(v  ).6 . (W/L) p 5 x ( /) = (W/L) n 3 x 6 x x = (.5.4./) (W/L) p = 3.5 x.5 = 5.5 for a V M of.5v 9/8/4 VLSI esign I;. Milenkovic 4 9/8/4 VLSI esign I;. Milenkovic 7 Switching Threshold V M where V in = (both PMOS and NMOS in saturation since V S = V GS ) V M r /( + r) where r = k p V STp /k n V STn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want V M = / (to have comparable high and low noise margins), so want r (W/L) p k n V STn (V M V Tn V STn /) (W/L) n = k p V STp ( V M +V Tp +V STp /) V M (V) Simulated Inverter V M. ~3.4 (W/L) p /(W/L) n Note: xaxis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3,.5 and gives V M s of.v,.8v, and.3v Increasing the width of the PMOS moves V M towards Increasing the width of the NMOS moves V M toward 9/8/4 VLSI esign I;. Milenkovic 5 9/8/4 VLSI esign I;. Milenkovic 8
4 Noise Margins etermining V IH and V IL Impact of Process Variation on VTC Curve 3 V OH = V OL = VIL V M V in piecewise linear approximation of VTC VIH y definition, V IH and V IL are where d /dv in =  (= gain) NM H =  V IH NM L = V IL  pproximating: V IH = V M  V M /g V IL = V M + (  V M )/g So high gain in the transition region is very desirable ad PMOS Good NMOS Good PMOS ad NMOS Nominal process variations (mostly) cause a shift in the switching threshold 9/8/4 VLSI esign I;. Milenkovic 9 9/8/4 VLSI esign I;. Milenkovic CMOS Inverter VTC from Simulation um, (W/L) p /(W/L) n = 3.4 (W/L) n =.5 (min size) =.5V V M.5V, g = 7.5 V IL =.V, V IH =.3V NM L = NM H =. (actual values are V IL =.3V, V IH =.45V NM L =.3V & NM H =.5V) Output resistance lowoutput =.4kΩ highoutput = 3.3kΩ 9/8/4 VLSI esign I;. Milenkovic.5.5 Scaling the Supply Voltage.5 Gain= evice threshold voltages are evice threshold voltages are kept (virtually) constant kept (virtually) constant 9/8/4 VLSI esign I;. Milenkovic Gain eterminates gain V in.5.5 Gain is a strong function of the slopes of the currents in the saturation region, for V in = V M (+r) g (V M V Tn V STn /)(λ n  λ p ) etermined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing). 9/8/4 VLSI esign I;. Milenkovic Static CMOS Logic
5 CMOS Circuit Styles Threshold rops Static complementary CMOS  except during switching, output connected to either V or via a lowresistance path high noise margins full rail to rail swing VOH and VOL are at V and, respectively low output impedance, high input impedance no steady state path between V and (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) ynamic CMOS  relies on temporary storage of signal values on the capacitance of highimpedance circuit nodes simpler, faster gates increased sensitivity to noise 9/8/4 VLSI esign I;. Milenkovic 5 PUN S PN S V GS S  V Tn V GS S V Tp 9/8/4 VLSI esign I;. Milenkovic 8 In In Static Complementary CMOS Pullup network (PUN) and pulldown network (PN) PUN PMOS transistors only pullup: make a connection from to when (In,In, In N ) = Construction of PN NMOS devices in series implement a NN function In N In In PN (In,In, In N ) pulldown: make a connection from to when (In,In, In N ) = NMOS devices in parallel implement a NOR function In N NMOS transistors only + PUN and PN are dual logic networks 9/8/4 VLSI esign I;. Milenkovic 6 9/8/4 VLSI esign I;. Milenkovic 9 Threshold rops ual PUN and PN PUN PUN and PN are dual networks emorgan s theorems + = [!( + ) =!! or!( ) =! &!] = + [!( ) =! +! or!( & ) =!!] PN a parallel connection of transistors in the PUN corresponds to a series connection of the PN Complementary gate is naturally inverting (NN, NOR, OI, OI) Number of transistors for an Ninput logic gate is N 9/8/4 VLSI esign I;. Milenkovic 7 9/8/4 VLSI esign I;. Milenkovic 3
6 CMOS NN CMOS NOR NOR = NOR(,) = = = = = = = = = = = = 9/8/4 VLSI esign I;. Milenkovic 3 9/8/4 VLSI esign I;. Milenkovic 34 CMOS NN Complex CMOS Gate NN = NN(,) OUT =!( + ( + C)) C = = = = = = = = = = = = 9/8/4 VLSI esign I;. Milenkovic 3 9/8/4 VLSI esign I;. Milenkovic 35 CMOS NOR Complex CMOS Gate + C C OUT =!( + ( + C)) 9/8/4 VLSI esign I;. Milenkovic 33 9/8/4 VLSI esign I;. Milenkovic 36
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