EE115C Digital Electronic Circuits Homework #3


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1 Electrical Engineering Department Spring 1 EE115C Digital Electronic Circuits Homework #3 Due Thursday, April, E EIV Solution Problem 1 VTC and Inverter Analysis Figure 1a shows a standard CMOS inverter. However, during the process of manufacturing, the circuit was contaminated with a particle and the gate of the PMOS transistor got shorted to GND instead of being connected to the input. The contaminated inverter circuit could be modeled as shown in Figure 1b. Figure 1: CMOS Inverter. (Note: L indicates drawn channel length, assume x d = 15nm. 1A Find V OH, V OL, and V M for the inverters in Figures 1a and 1b. Sol: The circuit in Figure 1a: Regular CMOS inverter V OH =1.V V OL =V Little thinking experiment to validate this: Since we don t know V OH and V OL, let s start from V OH (1 somewhere above V M and calculate corresponding V OL (1. Pick another point for V OH ( > V OH (1, you will find V OH ( < V OL (1. Keep iterating until you hit bounds: V OH = V DD, V OL =. For V M (which we expect to be around V DD / =.5V, we can assume that both transistors are in saturation since V DSAT,N =.3V > V GT,N ; V DSAT,P =.4V > V GT,P
2 Electrical Engineering Department Spring 1 1 W I k ( V V (1 V ' N dn = N GSN THN + λn DSN LN = ( VM.17 (1.75 VM 1 W ' P IdP = kp ( VGSP VTHP (1 + λpvdsp LP = (1 VM. (1.6 (1 VM Set I dn = I dp and solve for V M V M =.49 V The circuit in Figure 1b: First iteration: V in = V OH (1 =1V Calculate Vout (V in =V OH = 1V Assuming V OL < V DSAT, NMOS is in linear mode, PMOS is in velsatutration Result: V out = V (1 OL =.119V Validate assumptions: NMOS: V DSN =.119V < V DSATN =.3V < V GTN =.83V PMOS: V DSATP =.4V < V GTP =.8V < V DSP =.881V (linear (velsat The value of V OL obtained here satisfies the assumption that NMOS is OFF when VOL is applied. Therefore: V OH = 1V V OL =.1V For V M, we can assume PMOS in linear, and NMOS in velsat regime ' WN VDSAT IdN = kn (( VGSN VTHN VDSAT (1 + λnvdsn LN = (( VM ( VM ' WP VDSP IdP = kp (( VGSP VTHP VDSP (1 + λpvdsp LP = 1.8 (1 V ((1..5 (1 V (1 +.6 (1 V Set I dn = I dp and solve for V M : V M =.64V M M M 1B Use SPECTRE to plot the VTC curves of the two inverters. Plot both VTCs and also the 45 o line (V in = V out all on one graph. Compare and discuss the differences in the VTC curves, robustness, and regeneration (assuming the output will connect to another inverter of the same kind of these two inverters.
3 Electrical Engineering Department Spring 1 Use following parameters for hand calculations: V DD = 1.V, V M =.5V, V DSAT =.3V for NMOS, and V DSAT =.4V for PMOS NMOS: V T =.17V, k n = 13μA/V, γ =.1V 1/, λ =.75V 1, Φ F =.6V PMOS: V T =.V, k p = 1μA/V, γ=.16v 1/, λ=.6v 1 Φ F =.6V Sol: Spectre simulation results are shown below: Figure  Pseudo NMOS Inverter VOUT volt Figure 1 CMOS inverter VIN volt Note: because the simulations are based on quite complex models, you may find a mismatch between the simulation results and simplified handcalculation from A. This is normal. Differences (simulation vs. handcalculations: VTC curves: V OL for the circuit in Fig.  is not zero, and the curve is shifted to the right from the curve of the CMOS inverter. This is because the PMOS is always turned on (recall the discussion in class about increased size of the PMOS transistor Robustness: NM L (Fig.  is smaller, hence the circuit in Fig. 1b is less robust NM L (Fig.  =.7V(V IL .7V(V OL =.V NM L (Fig. 1 =.6V(V IL .V(V OL =.6V In both circuits, NM H is greater than NM L Note: V IL values are estimated graphically. Regeneration: both circuits are good, because the absolute value of the gain in the transition region (slope of the VTC curve is greater than 1. However, the circuit in Fig. 1a regenerates faster due to a larger gain.
4 Electrical Engineering Department Spring 1 Problem Equivalent Resistance Consider NMOS device with W = 4nm and L = 1nm (effective L = 7nm. Using the resistor averaging technique discussed in class, Equations (3.4 and (3.43 from textbook, and parameters from Hw / Prob1, calculate R on as V DD changes from.4v1v in steps of.v. Compare the results of your hand calculations with simulation results. Assume V DSATn =.3V. Sol: We have the following from textbook equations and HW: λ =.795V 1 k' = 19.5 μ A/ V L V V eff th = 7nm =.168V dsatn =.3V W I k V V V V L 3 V 5 R = (1 λv dsat = ' (( dd th* dsat dsat / R dd on _ approx dd 4 Idsat 6 3 V 7 = (1 λv dd on _ exact dd 4 Idsat 9 Using the above data we get the following results. For R on_simulated we have two cases, with an average of two data point (VDD, VDD/ and an average over the entire range VDD VDD/. V DD [V] I DSAT (μa R ON_APPROX (KΩ R ON_EXACT (KΩ (KΩ R ON_SIM(range (KΩ R ON_SIM(points Discussion: The above solution approximates λ as a single value. From home work, we know that λ varies significantly with V GS. In digital circuits, V GS is often equal to V DD. Thus we need to consider different values of λ for calculation of R ON for different supply voltages. V GS [V] λ [1/V]
5 Electrical Engineering Department Spring 1 (Note: Value for V GS =.6 and.8 V are updates from simulations. These were not present in solution to Q.1C Home work Let us look at the results with these refined values of λ V GS [V] R ON APPROX R ON EXACT R ON SIM(points 7.79 K R ON SIM(range R ON is negative for.4v and significantly under estimates the delay at.6v! Did we not expect to get a better match with the new values λ? Here is the catch: The formulae used for calculation of R ON (approximate and exact, assume that the transistor is in velocity saturated mode of operation for the entire range V DD to V DD /. While this assumption is true for.8v and 1V, it is not valid at.6 V and.4 V. Hence we see that the model does not give reasonable values for R ON at.4 and.6 V. On the other hand, the results of the model and simulations are comparable for.8 V and 1 V supplies. Problem 3 Inverter in Subthreshold The inverter below, operates with V DD =.15 V and is composed of V tn = V tp =. V devices. The devices have identical I and n but the channel modulation constants are different (λ n =.75V 1, λ p = .6V 1, n = 1.5 and kt/q = 6 mv. a Calculate the switching threshold (VM of this inverter. Sol: Both devices are in the subthreshold region (V DD < V T I = I DN DP V GSN V DSN V GSP V DSP n( kt/ q ( kt/ q n( kt/ q ( kt/ q (1 (1 + λn DSN = (1 (1 + λ P DSP V M V M V M V M n( kt/ q ( kt/ q n( kt/ q ( kt/ q + λn M = + λ P M Ie e V Ie e V Ie (1 e (1 V Ie (1 e (1 (.15 V We can solve the above equation for V M using a math solver. You can take the following approach: plot I DN and I DP and as function of V M and find out the intersection point of these two curves this value corresponds to V M. V M =.75 V
6 b Calculate V IL and V IH of the inverter. (hint: equation 5.1 in textbook.15v.4v Electrical Engineering Department Spring 1 V in V out Figure 3 Hint: Use the subthreshold voltagecurrent relation. Sol: V IH = V M V M /g V IL = V M + (V DD V M /g From equation 5.1: VDD 1 φ T g = e 1 n = 11.6 V IH =.75.75/( 11.6 =.8V, V IL = V M + (V DD V M /g =.68V V IH =.8 V V IL =.68 V
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