Lecture 13  Digital Circuits (II) MOS Inverter Circuits. March 20, 2003


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1 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS inverter with currentsource pullup 3. Complementary MOS (CMOS) Inverter Reading assignment: Howe and Sodini, Ch. 5, 5.3
2 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 132 Key questions What are the key design tradeoffs of the NMOS inverter with resistor pullup? How can one improve upon these tradeoffs? What is special about a CMOS inverter?
3 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture NMOS inverter with resistor pullup (cont.) V = V OUT =V DS V OH =V MAX = R I R slope= A v (V M ) I D V OUT V M V OUT =V IN V IN CL V OL =V MIN 0 0 V T V M VDD V IN =V GS V IL V IH Noise margins: NM L = V IL V OL = V M V MAX V M A v (V M ) V MIN 1 NM H = V OH V IH = V MAX V M (1 A v (V M ) ) V MIN A v (V M ) Need to compute A v (V M ).
4 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 134 Smallsignal equivalent circuit model at V M (transistor in saturation): R G v in v gs gm v gs D r o v out S v in gm v in (r o //R) v out v out = g m v in (r o //R) Then: Then: A v = v out v in = g m (r o //R) g m R A v (V M ) = g m (V M )R From here, get NM L and NM H using above formulae.
5 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 135 Dynamics C L pulldown limited by current through transistor [will study in detail with CMOS] C L pullup limited by resistor (t PLH RC L ) pullup slowest V IN : LO HI R C L V OUT : HI LO V IN : HI LO R C L V OUT : LO HI pulldown pullup
6 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 136 Inverter design issues: noise margins A v R RC L slow switching g m W big transistor (slow switching at input) Tradeoff between speed and noise margin. During pullup, need: high current for fast switching, but also high resistance for high noise margin. use current source as pullup.
7 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture NMOS inverter with currentsource pullup IV characteristics of current source: i SUP v SUP i SUP I SUP 1 r oc _ v SUP Equivalent circuit models: i SUP v SUP I SUP roc r oc _ largesignal model smallsignal model high current throughout voltage range: i SUP I SUP high smallsignal resistance, r oc.
8 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 138 NMOS inverter with currentsource pullup: i SUP =I D load line i SUP I SUP V GS = V OUT V GS =V IN V IN C L V GS =V T 0 0 V DS Transfer characteristics: V OUT 0 0 VDD V T V IN High r oc high noise margin
9 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 139 Dynamics: i SUP i SUP V IN : LO HI C L V OUT : HI LO V IN : HI LO C L V OUT : LO HI pulldown pullup Faster pullup because capacitor charged at constant current.
10 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 1310 PMOS as currentsource pullup IV characteristics of PMOS: S G IDp D IDp IDp saturation VSGp VSGp=VTp VSDp VTp VSGp Note: enhancementmode PMOS has V Tp < 0. In saturation: I Dp (V SG V Tp ) 2
11 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 1311 Circuit and loadline diagram of inverter with PMOS current source pullup: I Dp =I Dn PMOS load line for V SG = V B V B V OUT V IN C L V IN 0 0 V OUT Transfer function: V OUT NMOS cutoff PMOS triode NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation 0 0 VDD V Tn V IN
12 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 1312 Noise margin: compute V M = V IN = V OUT compute A v (V M ) At V M both transistors saturated: I Dn = W n 2L n µ n C ox (V M V Tn ) 2 And: I Dp = W p 2L p µ p C ox ( V B V Tp ) 2 Then: I Dn = I Dp V M = V Tn µ p W p L p µ n W n L n ( V B V Tp )
13 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 1313 Smallsignal equivalent circuit model at V M : S2 v sg2 =0 g mp v sg2 r op G2 D2 D1 G1 v in v gs1 g mn v gs1 r on v out S1 v in gmn v in r on //r op v out A v = g mn (r on //r op )
14 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 1314 NMOS inverter with currentsource pullup allows fast switching with high noise margins. But... when V IN =, there is a direct current path between supply and ground power consumption even if inverter is idling. I Dp =I Dn PMOS load line for V SG = V B V B V OUT :LO V IN V IN :HI C L 0 0 V OUT Would like to have current source that is itself switchable, i.e., it shuts off when input is high CMOS!
15 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture Complementary MOS (CMOS) Inverter Circuit schematic: V IN V OUT C L Basic operation: V IN =0 V OUT = V GSn =0<V Tn NMOS OFF V SGp = > V Tp PMOS ON V IN = V OUT =0 V GSn = >V Tn NMOS ON V SGp =0< V Tp PMOS OFF No power consumption while idling in any logic state.
16 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 1316 Key conclusions In NMOS inverter with resistor pullup: tradeoff between noise margin and speed. Tradeoff resolved using currentsource pullup: use PMOS as current source. In NMOS inverter with currentsource pullup: if V IN = HI, power consumption even if inverter is idling. Complementary MOS: NMOS and PMOS switch alternatively no power consumption while idling.
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