9/18/2008 GMU, ECE 680 Physical VLSI Design


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1 ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design 1
2 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational Sequential Output = f(in) Output = f(in, ( Previous In) 29/18/2008 GMU, ECE 680 Physical VLSI Design
3 Static CMOS Circuit t every yp point in time (except during the switching transients) each gate output is connected to either V DD or V ss via a lowresistive path. The outputs t of fthe gates assume at all times thevalue of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. 39/18/2008 GMU, ECE 680 Physical VLSI Design
4 Static Complementary CMOS V DD In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only F(In1,In2, InN) PUN and PDN are dual logic networks 49/18/2008 GMU, ECE 680 Physical VLSI Design
5 Example Gate: NND 59/18/2008 GMU, ECE 680 Physical VLSI Design
6 Example Gate: NOR 69/18/2008 GMU, ECE 680 Physical VLSI Design
7 Constructing a Complex Gate V DD V DD C D C F SN1 D F C SN4 SN2 SN3 D F (a) pulldown network (b) Deriving the pullup network hierarchically by identifying subnets D C (c) () complete gate 79/18/2008 GMU, ECE 680 Physical VLSI Design
8 Properties of Complementary CMOS Gates High noise margins: V OH and V OL are at V DD and GND, respectively. OH OL DD No static power consumption: There never exists a direct path between V DD and V SS (GND) in steadystate mode. Comparable rise and fall times: (under appropriate sizing conditions) 89/18/2008 GMU, ECE 680 Physical VLSI Design
9 CMOS Properties Full rail to rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless lways a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors 9/18/2008 GMU, ECE 680 Physical VLSI Design
10 Switch Delay Model R eq R p R p R p R p R n C L R n C L R p C int R n R n C L NND2 R n Cint INV NOR2 10 9/18/2008 GMU, ECE 680 Physical VLSI Design
11 Input Pattern Effects on Delay (consider a NND gate with and input) R p R p C L Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 R p /2 C L R n one input goes low R n C int g delay is 0.69 R p C L High to low transition both inputs go high delay is R n C L 11 9/18/2008 GMU, ECE 680 Physical VLSI Design
12 Delay Dependence on Input Patterns ==1 0 Input Data Delay Pattern (psec) == Voltag ge [V] =1, =1 0 =1, = = 0 1, =1 50 =1 0, =1 == =1, = time [ps] = 1 0, =1 57 NMOS = 0.5μm/0.25 μm PMOS = 0.75μm/0.25 μm C L = 100 ff 12
13 Transistor Sizing (assume inverter Wp/Wn = 2) R p R p R p 2 R n C L 4 R p C int 2 R R n n R n C L Cint /18/2008 GMU, ECE 680 Physical VLSI Design
14 Transistor Sizing a Complex CMOS Gate 4 3 C D 4 6 OUT = D + ( + C) 2 D 1 2 C /18/2008 GMU, ECE 680 Physical VLSI Design
15 Fan In Considerations C D C C 3 C 2 C L Distributed RC model (Elmore delay) t phl = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) D C 1 Propagation delay deteriorates rapidly as a function of fan in quadratically in the worst case. 15 9/18/2008 GMU, ECE 680 Physical VLSI Design
16 t p as a Function of Fan In p 1250 quadratic (psec) t phl t p Gates with a fan in greater than 4 should be avoided. t p fan in t plh linear 16
17 t p as a Function of Fan Out p t p NOR2 t p NND2 ll gates have the same drive current. (psec) t p INV t p Slope is a function of driving strength eff. fan out 17
18 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan in of n requires 2n (n N type + n P type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N type + 1 P type) transistors 9/18/2008 GMU, ECE 680 Physical VLSI Design
19 Dynamic Gate M p M p Out Out In 1 In 2 In 3 PDN C L C M e M e Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) 19 9/18/2008 GMU, ECE 680 Physical VLSI Design
20 Dynamic Gate M p off M p on 1 Out Out In 1 In 2 In 3 PDN C L (()+C) C M e M e off on Two phase operation Precharge ( = 0) Evaluate ( = 1) 9/18/2008 GMU, ECE 680 Physical VLSI Design
21 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Non ratioed sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (Cout) no I sc, so all the current provided by PDN goes into discharging C L 21 9/18/2008 GMU, ECE 680 Physical VLSI Design
22 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) no glitching higher transition probabilities extra load on PDN starts to work as soon as the input signals exceed V V V d V l V V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock 22 9/18/2008 GMU, ECE 680 Physical VLSI Design
23 Issues in Dynamic Design 2: Charge Sharing M p redistributed (shared) over C L and C leading to reduced robustness Out Charge stored originally on C L is C L =0 M e C C 23 9/18/2008 GMU, ECE 680 Physical VLSI Design
24 Charge Sharing Example Out C L =50fF C a =15fF a! C b =15fF C c =15fF C C C d =10fF 24 9/18/2008 GMU, ECE 680 Physical VLSI Design
25 Charge Sharing V DD case 1) if ΔV out < V Tn M p Out C L V DD = C L V out ( t) + C a ( V DD V Tn ( V X )) M a X C L ΔV out or = V out ( t) V DD = C a V ( C DD V Tn ( V X )) L = 0 M b C a case 2) if ΔV out > V Tn M e C b C a ΔV out V = DD C a + C L 25 9/18/2008 GMU, ECE 680 Physical VLSI Design
26 Solution to Charge Redistribution M p M kp Out M e Precharge internal nodes using a clock driven transistor (at the cost of increased area and power) 26 9/18/2008 GMU, ECE 680 Physical VLSI Design
27 Issues in Dynamic Design 3: ackgate Coupling =0 M p Out1 =1 C L1 C L2 Out2 =0 In =0 M e Dynamic NND Static NND 27 9/18/2008 GMU, ECE 680 Physical VLSI Design
28 ackgate Coupling Effect 3 2 Out1 1 0 In Out Time, ns 28
29 Issues in Dynamic Design 4: Clock Feedthrough Coupling between Out and input of the precharge device due to the gate to M p draincapacitance. So voltage of Outcan Out rise above V DD. The fast rising (and falling edges) of the clock couple to Out. C L M e 29 9/18/2008 GMU, ECE 680 Physical VLSI Design
30 Clock Feedthrough Out 2.5 Clock feedthrough In 1 In In 3 In In & Out Time, ns 1 Clock feedthrough 30 9/18/2008 GMU, ECE 680 Physical VLSI Design
31 Other Effects Capacitive coupling Substrate coupling Minority i charge injection i Supply noise (ground bounce) 31 9/18/2008 GMU, ECE 680 Physical VLSI Design
32 Cascading Dynamic Gates V In M p Out1 M p Out2 In M e M e Out1 V Tn Out2 ΔV t Only 0 1 transitions allowed at inputs! 32 9/18/2008 GMU, ECE 680 Physical VLSI Design
33 Domino Logic M p Out M p In 1 In 2 PDN In 4 PDN M kp Out2 In 3 In 5 M e M e 33 9/18/2008 GMU, ECE 680 Physical VLSI Design
34 Why Domino? In i PDN In i PDN In i PDN In i PDN In j In j In j In j Like falling dominos! 34 9/18/2008 GMU, ECE 680 Physical VLSI Design
35 Properties of Domino Logic Only non inverting logic can be implemented Very high speed static inverter can be skewed, only L H transition Input capacitance reduced smaller logicaleffort 35 9/18/2008 GMU, ECE 680 Physical VLSI Design
36 Designing with Domino Logic V DD V DD V DD M p Out1 M p M r Out2 In 1 In 2 PDN In 4 PDN In 3 Can be eliminated! M e M e Inputs = 0 during precharge 36 9/18/2008 GMU, ECE 680 Physical VLSI Design
37 Footless Domino V DD V DD V DD M p O M p O M p O Out 1 Out In 1 In 2 In 3 In n Out n The first gate in the chain needs a foot switch Precharge is rippling short circuit current solution is to delay the clock for each stage 37 9/18/2008 GMU, ECE 680 Physical VLSI Design
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