CMOS Logic Gates. University of Connecticut 172


 Garey Goodwin
 2 years ago
 Views:
Transcription
1 CMOS Logic Gates University of Connecticut 172
2 Basic CMOS Inverter Operation V IN P O N O pchannel enhancementtype MOSFET; V T < 0 nchannel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and P O is linear. V OH. If V IN, N O is linear but P O is cut off. V OL 0. In either state, the DC power dissipation is negligible. CMOS is therefore very important for batterypowered applications such as watches, calculators, palmtops and laptops. In addition to the extremely low power dissipation, CMOS also exhibits better noise margins than NMOS with nearly as high packing density. University of Connecticut 173
3 CMOS Load Curve Analysis V IN 2.5V V T 0.6V K 0.5mA/V 2 P O I DD (ma) V IN 0V V IN 2.5V N O V T 0.6V K 0.5mA/V V IN 0.5V V IN 2V 0.4 The graphical load curve approach may be applied as with NMOS, but now the load curve is a function of V IN V IN 1V V IN 1.5V (V) University of Connecticut 174
4 CMOS Load Curve Analysis V IN P O N O I I DN DP University of Connecticut 175
5 CMOS Load Curve Analysis V IN 2.5V P O N O V T 0.6V K 0.5mA/V 2 V T 0.6V K 0.5mA/V 2 I DD (ma) V IN 1.5V e.g. if V IN 1.5V, then V V I V GSN GSP DD OUT 15. V 10. V 0. 04mA V University of Connecticut V IN 1.5V (V)
6 CMOS VTC V IN 2.5V P O N O V T 0.6V K 0.5mA/V 2 V T 0.6V K 0.5mA/V 2 (V) For the case of perfectlymatched transistors, i. e. V TP V TN and K P K N, the VTC is symmetric: V V V + V V V M DD IL IH DD NML V / 2 NMH University of Connecticut V IN (V)
7 CMOS VTC: Analytic Determination For V IN < V TN, the nmosfet is cut off but the pmosfet is linear, so For V TN < V IN < + V TN and V IN <  V TP, the nmosfet is saturated but the pmosfet is linear. Hence V I D OUT University of Connecticut 178
8 CMOS VTC: Analytic Determination In the vicinity of V IN V M, both MOSFET s are saturated. Thus, versus V IN cannot be determined without the knowledge of the channel length modulation parameters. For + V TN < V IN and + V TP < V IN <  V TP, the nmosfet is linear but the pmosfet is saturated. Hence V I D OUT Finally, for V IN >  V TP, the nmosfet is linear but the pmosfet is cut off so University of Connecticut 179
9 DC Current in CMOS 120 V IN 2.5V P O N O V T 0.6V K 0.5mA/V 2 V T 0.6V K 0.5mA/V 2 I DD (µa) For V IN < V TN, N O is cut off and I DD 0. For V TN < V IN < /2, N O is saturated. For /2 < V IN < +V TP, P O is saturated. For V IN > + V TP, P O is cut off and I DD V IN (V) Even though CMOS exhibits negligible DC dissipation in either logic state, appreciable power is dissipated during switching. University of Connecticut 180 0
10 Design of CMOS Transistors Suppose the minimum feature size is 0.5 µ m, t OX 70 Angstroms, and we want K P K N 0.5 ma/ V 2. k ' P ( W / L) P k ' N ( W / L) N University of Connecticut 181
11 CMOS Switching Speed Consider a symmetric CMOS inverter with a lumped capacitive load C L. Suppose the input voltage rises abruptly from 0 to. N O is saturated until drops to  V T. During this time, constant current flows in N O : I DN N O becomes linear when  V T at t T D1. T D1 University of Connecticut 182
12 CMOS Switching Speed Once drops to  V T, N O moves into the linear region of operation. To a first approximation, I DN VOUT 1 I where average value of R R V DN Now if N O is linear, then DN DN OUT I DN I V DN OUT University of Connecticut 183
13 CMOS Switching Speed If starts at  V T and ends up at zero, then the average value of the partial derivative is approximately 1 R DN Using the ohmic approximation for N O, we have a simple RC circuit: VOUT ( t) Then reaches the 50% point ( /2) at t T D1 + T D2, where T D 2 University of Connecticut 184
14 CMOS Switching Speed The hightolow propagation time is t PHL T D1 + T D2. Moreover, if the gate is perfectly symmetric, then t PLH t PHL. Thus t P Therefore the propagation delay is proportional to the load capacitance and inversely proportional to the K values for the (matched) transistors. For a fixed capacitive load, we need to scale up the K values to improve the switching speed. University of Connecticut 185
15 Loading of CMOS V IN 2.5V P O N O V T 0.6V 2.2µ m/ 0.5µ m V T 0.6V 0.9µ m/ 0.5µ m Suppose that K N K P 0.5 ma / V 2. 2 W KP 05. ma / V ' 2 L k ma / V P P W KN 0. 5mA / V ' L k mA / V C OXP C OXN C IN C L University of Connecticut 186
16 SPICE Transient Response V 2.5V P O V IN N O C L 2. 5V K K 05. ma / V V V 0. 6 V C t DD P P TP L N TN 78 f F ps 150 (SPICE) 120ps (calculated) 2 output voltage input voltage time (ns) University of Connecticut 187
17 CMOS Power Dissipation Under static (DC) conditions, the power dissipation is minimal (typically < 10 µw / gate). Under switching conditions, there is significant power dissipation. This is because the load capacitance is charged and discharged through dissipating elements (MOSFETs). During a lowtohigh transition, current flows from as the load capacitance is charged from 0V to. The total integrated current is equal to C L, in coulombs. During a hightolow transition, current flows to ground as the load capacitance is discharged from to 0V. The total integrated current is equal to C L, in coulombs. To avoid double counting, we should consider either current but not both. We will consider the ground current here. University of Connecticut 188
18 CMOS Power Dissipation V IN 2.5V P O N O C L Consider a symmetric CMOS inverter with a lumped capacitive load C L. Suppose the input voltage rises abruptly from 0 to. During T D1, N O is saturated until drops to  V T, and constant current flows in N O : I DN The total dissipation for 0 < t < T D1 is thus J 1 University of Connecticut 189
19 CMOS Power Dissipation Once drops to  V T, N O moves into the linear region of operation. J 2 But if the input voltage increases abruptly, the pchannel device switches off at t 0. Then, so that I DN J 2 University of Connecticut 190
20 CMOS Power Dissipation Therefore, the total energy dissipated for one cycle including a lowtohigh transition and a hightolow transition is J 1 + J 2 : J TOTAL The total dissipation is therefore P In the case of CMOS, the AC term is almost always dominant. For this reason, we can only talk about the PDP for CMOS if we specifiy the switching frequency. Note also that the switching frequency is generally less than the system clock frequency. University of Connecticut 191
21 CMOS Power Dissipation Consider a CMOS gate with a 2.5V supply, a 1 pf load, and 1 µ W DC dissipation 2.5V 1 mw 100 mw V IN P O 10 mw N O C L 1 mw 1k 10k 100k 1M 10M 100M switching frequency (Hz) Without an external load, the dissipation increases with switching frequency due to internal capacitance. This effect is quantized by the dissipation capacitance. University of Connecticut 192
22 CMOS Power Delay Product If we neglect the DC dissipation, then V IN P O P V C f 2 DD L The propagation delay is approximately N O C L t P C 2 KV L DD Therefore the PDP is frequency dependent and approximately VDDCL f PDP 2 2 K Thus it is important to decrease but it is extremely important to decrease the load capacitance. University of Connecticut 193
23 CMOS Power Delay Product In terms of the device design parameters, V IN P O K N O C L If C L comprises N onchip loads, then C L Therefore the PDP is approximately PDP Now we know how to make better CMOS! University of Connecticut 194
24 CMOS Fanout Increasing the fanout increases t P. If C L comprises N onchip loads, then V IN P O C L N O C L The K values are both equal to K Therefore t P N MAX University of Connecticut 195
25 CMOS NAND Gate 4011 NAND (ca 1965 A.D.) V B 25/5 25/5 V 3 to 15V 20/5 DD t 85 to 330ns P aluminum 50 pf L 5µ m t 1000 Angst roms min OX V A 20/5 Function: If any input goes low, then the associated pmosfet turns on, the associated nmosfet turns off, and the output goes high. Form: CMOS requires two MOSFETs per input, so the packing density is slightly less than for NMOS. University of Connecticut 196
26 CMOS NOR Gate 4001 NOR (ca 1965 A.D.) V A V B 50/5 50/5 V 3 to 15V DD t 85 to 330ns P aluminum 50 pf L 5µ m t 1000 Angstroms min OX 10/5 10/5 Function: If any input goes high, then the associated pmosfet turns off, the associated nmosfet turns on, and the output goes low. Form: There are still two transistors per input. However, the NOR gate requires 1/3 more chip area than the NAND gate. University of Connecticut 197
27 74HCxx CMOS Family 1/4 74HC00 NAND V A V A V B V B 9/3 9/3 35/3 90/3 7/3 7/3 15/3 35/3 V 4. 5 to 5. 5V t DD L 3µ m t P 600 Angstroms polysilicon gates P min OX DC 2.5µ W 15 pf V T 1V University of Connecticut 198
28 74HCxx CMOS Family: VTC 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 1/6 74HC04 HEX INVERTER Double buffering makes the VTC very sharp, thus increasing the external noise margins. Do you see why? 2.3V 2.5V 2.7V 4.33V 0.00V 2.50V 2.50V 0.67V 5.00V 5.00V 2.50V 0.00V University of Connecticut 199
29 74HCxx CMOS Family: VTC /6 74HC04 HEX INVERTER The external noise margins are both essentially 2.5 V. The noise margins for the first stage alone are both 1.9 V University of Connecticut V IN 200
30 74HC CMOS Dynamic Response For all three stages, the process transconductance parameters are k ' N 2 k ' P 2 The oxide capacitance per unit area is C OX A University of Connecticut 201
31 74HC CMOS Dynamic Response 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For stage A, K PA K C t NA LA PA University of Connecticut 202
32 74HC CMOS Dynamic Response 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For stage B, K PB K C t NB LB PB University of Connecticut 203
33 74HC CMOS Dynamic Response 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For stage C, K PC K C t NB LC PB University of Connecticut 204
34 74HC CMOS Dynamic Response 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For the doublebuffered gate, the total propagation delay is the sum of the individual delays: t P 0.8 ns 0.5 ns 13.8 ns University of Connecticut 205
35 74HC CMOS Dissipation 5V 9/3 35/3 90/3 V IN 3.5/3 15/3 35/3 C L 15 pf For the doublebuffered gate, the energy dissipated per switching cycle is J TOT University of Connecticut 206
36 CMOS IC Fabrication polysilicon gate n+ n+ p+ p+ p well n well phosphosilicate glass (PSG) metal thick field oxide n substrate or epitaxial layer thin gate oxide The twin well (or twin tub) process is used for stateoftheart CMOS fabrication. Modern improvements in the process include trench isolation, silicided gates, and the use of n+ buried layers. In BICMOS, NPN bipolar transistors are fabricated alongside p MOSFETs and nmosfets. University of Connecticut 207
37 Latchup in CMOS polysilicon gate thin gate oxide phosphosilicate glass (PSG) n+ n+ p+ p+ p well n well metal thick field oxide n substrate or epitaxial layer There are parasitic bipolar junction transistors inherent in the CMOS structure. Worse yet, the combination of a PNP and an NPN can form a PNPN device, which is a thyristor (or silicon controlled rectifier, SCR). Once turned on, the thyristor latches, and does not turn off after external bias is removed from the inner P and N regions. Once latched, the parasitic thyristor carries a large, steady, and usually destructive current from to ground. University of Connecticut 208
38 Latchup in CMOS n+ n+ p+ p+ Q 1 p well Q 2 Q 3 n well Q 4 CMOS inverter circuit with parasitics: P O n substrate or epitaxial layer Q 2 Q 4 With a low output, Q 2 and Q 4 can latch on. With a high output, Q 1 and Q 3 can latch on. Latchup can be prevented by reducing the parasitic resistances and by reducing the betas of the parasitic bipolar transistors. V IN N O Q 3 Q 1 University of Connecticut 209
39 CMOS and Static Discharge diode protection circuitry bonding pad to CMOS circuitry Destructive oxide breakdown occurs at 5V for t OX 50 Angstroms. For a 0.25 µm x 1 µm gate, this corresponds to a charge of 1.7 femto coulombs, or about 10,000 electrons! Casual contact with humans or between leads can permanently damage CMOS if proper precautions are not taken. Diode protection circuitry, conductive packaging, and grounding straps have minimized this problem. University of Connecticut 210
40 Full Scaling of CMOS Full Scaling means that all voltages and dimensions are scaled by a factor of 1/s, where s > 1. C K OX t P ε µ n ε t OX t OX 2C KV 2 DD WL OX OX W L L DD P V C f L Power Density is scaled by is scaled by is scaled by is scaled by is scaled by Full scaling provides a DRAMATIC improvement in performance for CMOS, and even reduces the power density in watts per square centimeter. University of Connecticut 211
41 CMOS Constant Voltage Scaling Constant Voltage Scaling means that all dimensions are scaled by a factor of 1/s, where s > 1, but the voltages are unchanged. C K OX t P ε µ n ε t OX t OX 2C KV 2 DD WL OX OX W L L DD P V C f L Power Density is scaled by is scaled by is scaled by is scaled by is scaled by Constant voltage scaling is easier for the customer, but increases the power density. University of Connecticut 212
42 CMOS: Complex Logic Functions 20/2 20/2 20/2 20/2 V C 8/2 V D 8/2 V A 8/2 V B 8/2 The ANDORINVERT function can be achieved easily in CMOS using 2N transistors for N inputs. A C B D AC + BD University of Connecticut 213
43 CMOS: Complex Logic Design CIRCUIT DESIGN ANDing is achieved by series stacks of nmosfets and parallel connection of pmosfets. ORing is achieved by paralleling nmosfets and the series stacking of pmosfets. MOSFET DESIGN For the inverter, (W P / L P ) 2.5(W N / L N ). (e.g., 10 / 2 and 4 / 2) For the AOI gate, W L N N m W N L AOI N INVERTER where m is the number of series nmosfets in the longest pulldown path and n is the number of series pmosfets in the longest pullup path. (in the example pictured, m 2, and n 2) University of Connecticut 214 W L P P n W P L AOI P INVERTER
44 Pseudo NMOS Logic Similar to NMOS, w/ pmosfet pullup X M PL pulldown network OUT Efficient realization of complex logic functions Improved packing density Disadvantage? University of Connecticut 215
45 Dynamic CMOS M PPRE CLK precharge evaluate precharge evaluate OUT IN M NO V IN CLK M NEVAL Dynamic CMOS Inverter t University of Connecticut 216
46 Dynamic CMOS M PPRE M PPRE X pulldown network OUT X pullup network OUT CLK M NEVAL CLK M NEVAL University of Connecticut 217
47 Dynamic CMOS Can t be Cascaded! CLK M PPREA M PPREB OUT A A M NOA B M NOB B CLK M NEVALA M NEVALB OUT t University of Connecticut 218
48 Domino Logic M PPRE M PPRE M PPRE A pulldown network B pullup network C pulldown network OUT CLK M NEVAL CLK M NEVAL CLK M NEVAL University of Connecticut 219
CMOS Logic Gates. University of Connecticut 181
CMOS Logic Gates University of Connecticut 181 Basic CMOS Inverter Operation V IN P O N O pchannel enhancementtype MOSFET; V T < 0 nchannel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationStep 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since
Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M  0 > V M  V Tn V SDp = V DD  V M = (V DD  V M ) V Tp Equate drain
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationEE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 > ESD PROTECTION CIRCUITS (INPUT PADS) > ONCHIP CLOCK GENERATION & DISTRIBUTION > OUTPUT PADS > ONCHIP NOISE DUE TO PARASITIC INDUCTANCE > SUPER BUFFER
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More information1OF8 DECODER/DEMULTIPLEXER HighSpeed SiliconGate CMOS
1OF8 DECODER/DEMULTIPLEXER HighSpeed SiliconGate CMOS The IN74AC138 is identical in pinout to the LS/ALS138, HC/HCT138. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationNTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate Description: The NTE4501 is a triple gate device in a 16 Lead DIP type package constructed with MOS P
More informationCMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) ReadOnly Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 CMOS
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationEE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More information1OF8 DECODER/DEMULTIPLEXER HighSpeed SiliconGate CMOS
1OF8 DECODER/DEMULTIPLEXER HighSpeed SiliconGate CMOS The IN74ACT138 is identical in pinout to the LS/ALS138, HC/HCT138. The IN74ACT138 may be used as a level converter for interfacing TTL or NMOS
More informationBCDTODECIMAL DECODER HIGHVOLTAGE SILICONGATE CMOS IW4028B TECHNICAL DATA
TECHNICAL DATA BCDTODECIMAL DECODER HIGHOLTAGE SILICONGATE CMOS IW4028B The IW4028B types are BCDtodecimal or binarytooctal decoders consisting of buffering on all 4 inputs, decodinglogic gates,
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationVLSI GATE LEVEL DESIGN UNIT  III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT  III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More information2 Input NAND Gate L74VHC1G00
Input NAND Gate The is an advanced high speed CMOS input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
More informationVLSI VLSI CIRCUIT DESIGN PROCESSES P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI VLSI CIRCUIT DESIGN PROCESSES P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) SYLLABUS UNIT II VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 m CMOS Design
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM
More informationLecture 4: CMOS review & Dynamic Logic
Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full railtorail swing high noise margins Logic levels not dependent
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από
More informationEECS 141 F01 Lecture 17
EECS 4 F0 Lecture 7 With major inputs/improvements From MaryJane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationNTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder
NTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder Description: The NTE4514B (output active high option) and NTE4515B (output active low option) are two output options of a 4
More informationChapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter
Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationFeatures Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4025 CD4023BM CD4023BC Buffered Triple 3Input NAND Gate CD4025BM CD4025BC Buffered Triple 3Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
More informationLow Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 08 MOS Inverters  III Hello, and welcome to today
More informationNTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register
NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package
More informationCPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
More informationS No. Questions Bloom s Taxonomy Level UNITI
GROUPA (SHORT ANSWER QUESTIONS) S No. Questions Bloom s UNITI 1 Define oxidation & Classify different types of oxidation Remember 1 2 Explain about Ion implantation Understand 1 3 Describe lithography
More informationDual D FlipFlop with Set and Reset HighSpeed SiliconGate CMOS
TECHNICAL DATA IN74ACT74 Dual D FlipFlop with Set and Reset HighSpeed SiliconGate CMOS The IN74ACT74 is identical in pinout to the LS/ALS74, HC/HCT74. The IN74ACT74 may be used as a level converter
More information3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]
Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an nchannel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3
More informationBased on slides/material by. Topic 34. Combinational Logic. Outline. The CMOS Inverter: A First Glance
ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationCircuit A. Circuit B
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 19, 2006 by Karl Skucha (kskucha@eecs) Borivoje Nikolić Homework #9
More informationNTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX =  4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationCMOS Inverter. Performance Scaling
Announcements Exam #2 regrade requests due today. Homework #8 due today. Final Exam: Th June 12, 8:30 10:20am, CMU 120 (extension to 11:20am requested). Grades available for viewing via Catalyst. CMOS
More informationMODULE III PHYSICAL DESIGN ISSUES
VLSI Digital Design MODULE III PHYSICAL DESIGN ISSUES 3.2 Powersupply and clock distribution EE  VDD P2006 3:1 3.1.1 Power dissipation in CMOS gates Power dissipation importance Package Cost. Power
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationCMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits
Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by
More informationCMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = > = When = > = In between, depends on transistor size and current
More informationOctal 3State Noninverting Transparent Latch
SL74HC73 Octal 3State Noninverting Traparent Latch HighPerformance SiliconGate CMOS The SL74HC73 is identical in pinout to the LS/ALS73. The device inputs are compatible with standard CMOS outputs;
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM
More informationDigital Integrated Circuits 2nd Inverter
Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response
More informationChapter 5 CMOS Logic Gate Design
Chapter 5 CMOS Logic Gate Design Section 5. To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter FirstOrder DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More information