VLSI Circuit Design (EEC0056) Exam

Transcription

1 Mestrado Integrado em Engenharia Eletrotécnica e de omputadores VLSI ircuit esign (EE0056) Exam 205/6 4 th year, 2 nd sem. uration: 2:30 Open notes Note: The test has 5 questions for 200 points. Show all your work. Technology parameters: MOS 0.25 µm. W min =0.3 µm, L min =0.25 µm. V =2.5 V. The template inverter has L n =L p =L min, W n =W min, W p =2 W min.. complex MOS gate implements the function Y = ( + ) + E. [5] (a) raw the circuit schematic of the gate and size all transistors so that the gate has the same put drive as the reference inverter. [20] (b) Show the stick diagram of the gate. Use only one P+ and one N+ diffusion (with breaks). Use the Euler path method to derive the lay. 2. onsider the circuit described in the HSPIE netlist shown in the annex. [5] (a) raw the top-level schematic with annotated nodes and components. [0] (b) Explain how the HSPIE simulation determines V IL and V IH as a function of β = W p /W n. [0] (c) The figure below the netlist shows the result of running HSPIE. What are the noise margins for β = 5? Is this the most balanced situation? 3. onsider the logic gate shown in the figure, which has been sized for equal rise and fall times. ssume p inv = and that the capacitance of each input (,, or ) is in [5] (a) etermine the corresponding oolean function. [0] (b) etermine the logic effort of each input. [20] (c) ssume an put load of L = 200 in. Suppose that you can add any number of inverters between the gate and the load. Size the chain for minimum delay. [0] (d) What is the minimum delay for the optimum design (in units of τ)? [0] (e) Transistor width is directly proportional to gate capacitance (i.e., gate capacitance can be used to measure transistor width, and is also therefore proportional to circuit size). etermine the total transistor width of the chain in terms of in. The complex logic gate can be implemented using NN2, NOR2 and inverters as follows: João anas Ferreira Page of 3 Exam

2 [5] (f) ssuming the same in as used previously (for each input of a NOR2 gate), size the chain for minimum delay (you can add any number of inverters). [5] (g) For the new design, determine the minimum delay and the total transistor width of the chain in terms of in. When would you use the second version? 4. The figure shows the schematic for an edge-triggered flip-flop that combines a dynamic front-end and a static back-end. P X P2 Q inv6 Q N N2 S nand inv4 inv3 N4 N5 inv5 N3 inv inv2 [0] (a) omplete the timing diagram for the situation in which a zero gets stored in the flip-flop (which previously held a one). X S Q Q [20] (b) Explain the basic operation of the flip-flop, considering both the pre-charge and the evaluation phases. Show that the flip-flop has zero (or negative) setup time. [0] (c) Explain how the circuit can be changed to embed a logic function. Exemplify this ability by embedding a two-input OR function in the gate (with inputs and instead of the single input ). [Hint: consider omino logic.] [5] 5. Explain the purpose of three types of constraints that may be used with logic synthesis tools. (ata for problem 2 on the next page) João anas Ferreira Page 2 of 3 Exam

3 nnex: Netlist and data for problem 2.param supply=2.5 step=0.00 beta=2.option accurate post brief.glol vdd Vdd vdd 0 = supply.subckt aoi a b c M0 pint a vdd vdd PMOS L=250nm W= beta*300nm M pint b vdd vdd PMOS L=250nm W= beta*300nm M2 c pint vdd PMOS L=250nm W= beta*300nm M3 a nint gnd NMOS L=250nm W=300nm M4 nint b gnd gnd NMOS L=250nm W=300nm M5 c gnd gnd NMOS L=250nm W=300nm.ends ** Input sources Vin in gnd = supply Vind ind in = step ** Gates X0 in vdd gnd aoi X0d d ind vdd gnd aoi * sweep. vin 0 supply step beta * measurements.measure vil find v(in) when par( (v(d)-v())/step )=- cross=.measure vih find v(in) when par( (v(d)-v())/step )=- cross=2.lib "cmos250.lib" TT.end put(v) : beta 2.0 VIH.75 (5.0,.6734) VIL.5.25 put(v).0 (5.0,.2079) beta João anas Ferreira Page 3 of 3 Exam

4 Solutions Problem (a) complex MOS gate that implements the function Y = ( + ) + E. 6 6 E Y E (b) possible Euler path is E. Y Y Vdd E Gnd Vdd Y metal poly active area E Gnd Problem 2 (a) The top-level netlist is shown next. vin + in a b c aoi X0 vind + ind a b c X0d aoi d João anas Ferreira Solutions Exam

5 (b) Gate instances X0 and X0d have the same constant values at inputs b and c (respectively, vdd and gnd). In this situation, their puts switch when the a input changes, producing an inverter-like VT (note that a analysis is specified). The a input of instance X0d is 0.00 V higher than the input of instance X0. This is equivalent to the point of the VT of the aoi gate for a slightly higher input (Vin+step). Therefore, the expression par( (v(d)-v())/step ) is an approximation of the slope of the VT of the aoi gate. The measurement statements determine the input voltage for which the slope of the VT equals, which is the condition that define V IL (the first time the slope is ) and V IH (the second time the slope is ). The sweep specifies that the analysis is repeated for values of β between 0. and 0 in increments of 0.05, giving the curves shown in the figure. (c) The noise margins for β = 5 are (using the values from the graph): NMH = V V IH = 2.5 V.67 V = 0.83 V NML = V IL =.2 V This is not the most balanced situation. For β = 3, we would have (by inspection of the graph): NMH V NML V Problem 3 (a) The function is Out = ( + )( + ). (b) ll inputs have the same logic effort: (c) For this path, we have the path effort H: g = g = g = g = in_gate in_inv = 6 3 = 2. G = 2, =, F = 200 H = GF = 400 From the table, the optimum number of stages is 5, the complex gate followed by 4 inverters. Therefore, ĥ = = 3.3 The input capacitance of the the four inverters is (starting with the one nearest the load): 4 = 200 in 3 = in 2 = 8.2 in = 5.49 in For confirmation, the input capacitance is ĥ = in ĥ = 8.2 in ĥ = 5.49 in ĥ =.66 in.66 in 2 ĥ =.00 in João anas Ferreira Solutions Exam

6 (d) To find the overall delay, we must estimate the parasitic delay of the complex gate. The minimum delay is then: p gate = p inv = 4 d = N ĥ + i p i = = (τ) (e) The total gate capacitance of the complex gate is 4 in, because the gate has 4 inputs. Therefore, the total gate capacitance (proportional to gate width) of the chain is tot = in ( ) = 89.7 in (f) For this path, we have the path effort H: G = 5 3 4, =, F = 200 H = GF = From the table, the optimum number of stages is still 5, so we need two additional inverters at the end of the chain. Therefore, the stage effort is ĥ = = 3.39 The input capacitance of the gates is (starting with the extra inverter): 2 = 200 in = 59 in nand = 7.40 in 4/3 ĥ inv = 6.84 in For confirmation, the input capacitance is 2.02 in 5/3 ĥ ĥ = 59 in ĥ = 7.40 in = 6.84 in ĥ = 2.02 in = 0.99 in in (g) The intrinsic delay of a NN2 or a NOR2 gate is 2. Therefore, the total delay is: d = N ĥ + i p i = = (τ) To calculate the total gate capacitance of the chain (total transistor width), we must account for all gate inputs. tot = in ( ) = 98.2 in The second design is faster (.025 ) than the first, but it is also bigger (.094 ). You would use the second design if speed is very important for the module using this gate and the chain is in the critical path. João anas Ferreira Solutions Exam

7 Problem 4 (a) The timing diagram is shown next (arrows are for explanation): X S Q Q Note that is a delayed version of. (b) [Note: a shorter explanation is acceptable.] The flip-flop samples input and produces put Q, the logic complement of. On the falling edge of, the circuit enters the pre-charge phase: node X is precharged high, cutting off node Q from the input stage. INV5 and INV6 constitute a static latch, that holds the previous values of Q and Q. (delayed clock) is also low, so node S is high and holds transistor N on. The evaluation phase starts with going high. If =0 (storing a zero) node X stays high (held by the INV4-INV5 latch). Node Q would remain low or be discharged by the series N4-N5, ensuring the Q is high. Three gate delays after rises, node S is driven low and turns N off. fterwards, any low-to-high transition on will not discharge node X (this defines the hold time). This fact provides the edge-triggered operation of the flip-flop. IF = at the start of the evaluation phase (storing a one), node X would discharge through N-N2-N3. The static latch INV4-INV5 would hold the value of X even if changed again to zero.the falling transition on X will turn P2 on and drive Q high. This transition would also ensure that node S is high (shutting off N after the discharge of X is unnecessary). The discharge of node X (the only change that can occur in the evaluation phase) starts as soon as = and =. Therefore, the setup time is zero. (In fact, the rising of might even occur just after the rising clock edge, which would provide a small negative setup time.) (c) The idea is to implement the complement of the desired function in the input pull-down network (as done with omino logic). In this case, put Q will be one if either or are one, allowing node X to discharge. The changes are marked in red. P X P2 Q inv6 Q N N2 N6 S nand inv4 inv3 N4 N5 inv5 N3 inv inv2 João anas Ferreira Solutions Exam

8 Problem 5 Several types of constraints might be used in the answer. For example (any three are acceptable):. minimum clock frequency (for sequential circuits): defines the minimum operating frequency of the circuit (sequential circuits only); 2. maximum delay (for combinational circuits): defines maximum worst-case propagation delay from any input to any put; 3. put capacitance: defines the maximum capacitive load expected at a given put; 4. driver strength: characterizes the gate that drives a given input; 5. external delays (input or put): specify the delays of input/put signals relative to the clock signal. João anas Ferreira Solutions Exam