Lecture 5. MOS Inverter: Switching Characteristics and Interconnection Effects

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1 Lecture 5 MOS Inverter: Switching Characteristics and Interconnection Effects

2 Introduction C load = (C gd,n + C gd,p + C db,n + C db,p ) + (C int + C g ) Lumped linear capacitance intrinsic cap. extrinsic cap.

3 First-Stage CMOS Inverter With Lumped Load Capacitance The question of inverter transient response is reduced to finding the charge-up and charge-down times of a single capacitance.

4 Delay-Time Definitions V 50% = V OL +0.5(V OH V OL ) =0.5(V OL + V OH ) τ P = ½ (τ PLH + τ PHL ) High-to-Low t PHL Low-to-High t PLH

5 Rise Time and Fall Time Rise Time t rise : output to rise from V 10% to V 90% Fall Time t fall : output to fall from V 90% to V 10%

6 Propagation Delay Calculation Estimate the average capacitance current during charge down and charge up, respectively.

7 A More Accurate Method C i D C load, p load dt dv 0 dt dv out out = i C = i = D, n i D, p i D, n

8 A More Accurate Method (Cont.) When the nmos transistor starts conducting, it initially operates in the saturation region. When the output voltage falls below (V DD V T,n ), the nmos starts to conduct in the linear region.

9 A More Accurate Method (Cont.) Saturation region Linear region

10 A More Accurate Method (Cont.) Qi t 1 = = t= t t= t ' t 0 ' 1 out OH T, n o k C n dt 2Cload ( V V = dv dt OH k = C n 2C ( V OH load T, n load ) V V V 2 V out T, n T, n = V = V V V ) out out OH 2 = V = V V OH OH V 1 ( i T, n D, n dv ) dv out out

11 A More Accurate Method (Cont.) At t = t 1, the output voltage will be equal to (V DD -V T,n ) and the transistor will be at the saturation-linear region boundary. t= t1 Vout = V50% 1 dt = Cload ( ) t= t1 ' dvout Vout = VOH VT, n i = 2C t t 1 1 τ t t PHL ' 1 ' 1 = load k n V V n out out C ( V = V = V OH 50% OH 2Cload = kn C = k ( V V OH load 2( V load V T, n T, n V ( k T, n n 1 V OH [ ) ( V [2( V T, n 2( V ln( ) 2V OH D, n OH 1 ln( ) 2( V T, n V V OH T, n T, n V V ) V OH T, n 50% out V V T, n ) V V out 4( V + ln( ) V ) V 50% OH 2 out OH ) ) dv ] out V + V ) T, n OL out V V out out = V = V 50% OH ) 1)] V T, n

12 Consider Inputs With Finite Slopes Assuming: Input has finite rise t r & fall time t f A cell s delay in the Library is often characterized by a table (e.g., 5x5) in terms of two circuit-dependent indexes - slopes of the input signals - extrinsic loading (related to no. of fanouts) slope Timing matrix loading

13 Reducing a Cell Delay Two Major Factors of Cell Delay The driving current The larger current, the shorter propagation delay The loading capacitance The larger output loading, the longer propagation delay Common Techniques for Speeding Up A Cell Increase V DD (I D increases) Use low-v T device (I D increases) May introduce a larger sub-threshold current Gate-sizing: increase the W/L ratio of the gate (I D increases)

14 Inverter Design with Delay Constraints Assumption: ignore the intrinsic capacitance in calculating the loading capacitance. Question: what s the min. W/L ratio to achieve a given speed? By the assumption, C load is regarded as a constant

15 Considering Intrinsic Capacitance = α 0 + α n W n + α p W p

16 Asymptotic Speed Limit by Sizing Due to the drain parasitic capacitance: Sizing up a transistor (i.e., increasing W n and W p ) will have a diminishing effect in reducing the propagation delay. Delay in terms of design parameter W n and W p Limit Delay: R = W p /W n

17 Example: Transient Response 50% reduction in t PHL when W n = 2 to 3.2 mm But almost no effect when W n = 10 to 20 mm

18 Example: Delay v.s. Channel Width Limit value is about 0.2 ns, Determined by technology-specific parameters, Independent of the extrinsic capacitance components

19 Optimum W n for Area-Delay Product Gate Sizing: is a trade-off for delay reduction by silicon area Question: What s a good balance between area and delay?

20 Another Side-Effect of Gate Sizing Sizing Up a Gate increases its fanin gates loading, slightly offseting the speed advantages Example Action: increase the size of gate G3 Side-Effect: the loading capacitances of G1 and G2 will increase, and therefore the delays across G1 and G2 increase too. A B C G1 G2 D E G3 F

21 Three-Stage Ring Oscillator When n is an odd no. Oscillation frequency 1 f = = T 1 2 n τ p

22 Interconnection Models Time of flight across the line: l/v, l is the length, v is the travel speed Inductance is important when signal rise/fall time comparable to time-offlight τ rise (τ fall ) < 2.5 (l / v) transmission-line model 2.5 (l / v) < τ rise (τ fall ) < 5 (l / v) either one τ rise (τ fall ) > 5 (l / v) lumped modeling

23 An RLCG Interconnection Tree

24 Typical Signal Waveforms

25 Interconnect in Submicron Design Interconnect delay begins to dominate the cell delay in the submicron designs

26 Typical Interconnection Length Long running wires need accurate wire models: - inter-module connections - global bus connections - clock distribution networks Probability Wire Length Chip Diagonal Length

27 Interconnect Segments

28 Interconnect Segment

29 Single Line Capacitance Two basic components (i) Parallel Capacitance: C pp (ii) Fringing Capacitance Fringing effects Width-to-height ratio W/H

30 Lateral (Inter-Wire) Capacitance Lateral cap.

31 Inter-Layer Capacitance Fringing cap. Fringing & overlap cap. Lateral cap. Parallel plate cap.

32 Double Metal CMOS Structure Only inter-layer cap. are shown

33 Inter-Layer Parasitic Cap. For 0.8 μm Inter-layer (vertical) capacitances - area cap. (parallel-plate cap.) - perimeter cap. (fringing cap.)

34 Summary Of Parasitic Capacitances Total Cap. Inter-layer cap. Inter-wire cap. C x Parallel-plate cap. C p-p Fringing cap.

35 Interconnect Resistance Estimation l R wire = r w t l = R sheet w Where r is resistivity t is the thickness r R sheet = t (sheet resistance)

36 Interconnect Delay Models RC Model t PLH ~ 0.69 RC Distributed RC Model (ladder network) T Model

37 Uniform RC Ladder Network assume R k =(R/N) C j =(C/N) For very large N

38 Example: Comparison of Models

39 Example: Comparison of Models input output with lumped RC model output with T model output with distributed RC model

40 Impact of Wire Length to Delay Using distributed RC model Assume that Unit length resistance is R Unit length capacitance is C Then the delay constant of a wire of k-unit length will be: RC N (N+1)/2 i.e., delay is quadratically proportional to the wire length For example, increasing a wire length by 10 times will approximately increase the delay by 100 times

41 Clock Skew Problem Definition Clock skew refers to the maximum clock arrival time difference of the flop-flops clock ports Impact clock skew may slow down the operating speed Clock skew minimization near zero clock-skew can be achieved in automatic place-and-route (APR) tools via proper buffer insertion can be done by adopting a regular clock tree structure (e.g., H-tree) enforced manually clock source H-tree clock nets clock sink

42 Example: Clock Skew Calculation Assume that: unit length capacitance is C unit length resistance is R the input gate capacitance of FF s clock port is C g the number labeled with each segment is the length Clock source 6 6 S A FF 1 2 B FF

43 Voltage & Current Outputs of Inverter V in V out

44 Energy Transfer at Charge-Up 1 Pavg = T 1 T = [ T 0 1 = [( C T 1 = CloadV T Q f = 1/ T P avg = / 2 V load C T 0 v( t) i( t) dt out 2 DD load ( C dv dt V 2 out V DD 0 load V DD 0 2 DD f ) dv dt T / 2 0 out ) dt + + ( V DD V T T / 2 out ( V C DD load V 1 2 out C )( C load V load 2 out dv dt ) out T T / 2 ] ) dt]

45 Lecture 6 Combinational MOS Logic Circuits

46 Introduction nmos Logic - NOR Gate - NAND Gate CMOS Logic Complex Logic Circuits Transmission Logic

47 Combinational Logic Circuit Boolean Operations are the basic building block of digital systems Positive logic convention Logic 1 represents Vdd Logic 0 represents a low voltage Important design concerns: DC Voltage Transfer Characteristic V OL, V th Dynamic Characteristics Silicon Area Static & Dynamic Power Dissipation

48 Two-Input nmos NOR Gate Pull-up network Pull output voltage to high when both inputs are low Pull-down network Pull output voltage to low when either input is high

49 Calculation of V OL Obviously, V OH = V DD Three conditions in calculating VOL V A = V OH, V B = V OL reduced to an inverter V A = V OL, V B = V OH reduced to an inverter (Equ. 7. 4) V A = V OH, V B = V OH both drivers are turned on V OL = Equ. 7. 8

50 Design Strategy for nmos NOR Gate Set a certain maximum V OL for the worst case (i.e., output voltage should be less than this value in normal operation) Worst case happens when only one input is high Set k driver,a = k driver,b = k R k load This design choice yields two identical drivers Find the proper channel W and L for each transistor When both inputs are logic-high, The output voltage is even lower than the required maximum V OL because lower equivalent driver-to-load k leads to a lower V OL

51 Generalized to Multiple Inputs Generalized n-input NOR Assume that The input voltages of all drivers are identical V GS,k = V GS for k=1,..,n Reduced to an inverter No body-effect in any driver Substrate-bias of depletion-type load is V SB = V out

52 Transient Analysis Lumped load capacitance is C load = C gd,a + C gd,b + C gd,load + C db,a + C db,b + C sb,load + C wire Valid even for single-input switching Slower than the equivalent inverter with the same k R

53 Two-Input NAND Gate

54 Equivalent Driver Transconductance Consider the only case as pull-down is turned ON V A = high (V OH ) and V B = high (V OH ) Ignore the body-effect of Driver A

55 Generalized to Multiple Inputs

56 Load Capacitance of NAND Gate (I) Consider Case (I) V A = high V B is from V OH to V OL Lumped load capacitance C load = C gd,load + C sb,load + C gd,a + C gs,a + C db,a + C sb,a + C gd,b + C db,b + C wire This cap. is conservative In reality, only a fraction of Internal node s capacitance is Reflected into C load

57 Load Capacitance of NAND Gate (II) Consider Case (II) V A is from V OH to V OL V B = V OH Lumped load capacitance C load = C gd,load + C sb,load + C gd,a + C db,a + C wire This cap. is smaller It means that output Low-to-high switching is Faster in this case (e.g., 30% faster) This property could be used for speed optimization

58 Example (2-Input nmos NAND Gate) Two switching events

59 Example: Output Waveforms For NAND-gate, Turning off the nmos closer to the output Results in a faster output LOW-to-HIGH transition

60 CMOS Two-Input NOR Gate

61 CMOS Two-Input NOR Gate V OH = V DD, V OL = 0V V A = V B = V OUT = V th I D = K n (V th -V T,n ) 2 V th = V T,n + (I D / K n ) 1/2 (7.32) From Fig , M3: linear region, M4: saturation for V in = V out If k n = k p, V tn = V tp, the switching threshold of the CMOS inverter is equal to V dd /2. the switching threshold of the NOR2 gate is (V dd + V T,n )/3, which is not equal to V dd /2

62 Switching Threshold Voltage n p tp DD n p Tn th n p tp DD n p Tn th p D tp th DD D D D SD tp th DD p D SD SD tp th DD p D k k V V k k V INR V k k V V k k V NOR V k I V V V I I I V V V V k I V V V V V k I + + = + + = = = = = = 1 ) ( ) ( 1 ) ( 2) ( 2 ) ) ( 2 ] ) [2( Q

63 Equivalent Inverter

64 Calculating Switching Threshold V th Definition: V A = V B = V out = V th NOR2 = Equivalent Inverter (pull-down k down = 2k n ) (pull-down k up = (k p /2) To achieve V DD /2 switching threshold: Set V T,n = V T,p and k p = 4k n

65 Internal Parasitic Capacitances

66 CMOS Two-Input NAND Gate Assume that (W/L) n,a = (W/L) n,a and (W/L) n,b = (W/L) n,b (From Eq. 7.37)

67 Impact of Body Effects on Series-Connected Transistor Chain V DD A B C D OUT A α 1pF B β C γ D The discharging current is limited by the uppermost transistor (the one controlled by A) because it has a larger V t due to Body Effects

68 Area Comparison Transistor Count for n-input logic gate nmos logic : (n+1) CMOS logic : (2n) Real silicon area is used for Transistor Signal Routing Contact Therefore, the disadvantage of CMOS in terms of silicon area may not be as worse as the transistor count suggests

69 Sample Layout of CMOS NOR2 Gate VDD nwell GND V A V B

70 Sample Layout of CMOS NAND2 Gate VDD GND V A V B

71 nmos Complex Logic A Boolean function W ( ) L Z = A(D+E) + BC OR operations are done by parallel-connected drivers AND operations are done by series-connected drivers Inversion is provided by the nature of MOS circuit equivalent = 1 W ( ) L B W ( ) L C + 1 W ( ) L A 1 + W ( ) L D 1 W + ( L ) E

72 Worst-Case Logic-Low Voltage V OL Various Paths from V DD to GND lead to different V OL A-D Class 1 A-E Class 1 B-C Class 1 A-D-E Class 2 A-D-B-C Class 3 A-E-B-C Class 3 A-D-E-B-C Class 4 Assume all (W/L) the same A larger path resistance leads to a larger V OL V OL1 > V OL2 > V OL3 > V OL4 where subscript denotes class number

73 Complex CMOS Logic Gates Dual Network Given a Boolean expression Dual network is obtained via the following operations: Each variable is replaced by its complement Change AND to OR operation, and vice-versa De-Morgan Law: f = Dual-function(f) Example f = (A(D+E) + BC) Dual-function(f) = [A + (D E ) ] (B + C ) CMOS Logic Use n-network s dual function as the p-network to replace the depletion-type nmos load

74 Graphical Method for Dual Network out A B P-network VDD out D E C GND

75 Example: CMOS Complex Gate V out = A(D+E) + BC

76 Example: Equivalency Rule ) ( 1 ) ( 1 1 ) ( 1 ) ( 1 ) ( 1 1 ) ( ) ( ) ( 1 ) ( ) ( ) ( 1 1 ) ( ) )( (,, = = = = + = = = C B A E D eq p C B A E D eq n L W L W L W L W L W L W L W L W L W L W L W L W C B A E D Z

77 Gate Matrix Layout Poly-gate ordering is important: An improper ordering may result in extra silicon area for diffusionto-diffusion separation Stick-Diagram Layout D A out GND E B C

78 Optimal Gate Ordering Euler Path Uninterrupted path that traverses each edge of a graph exactly once Minimum Layout (without any diffusion break) Gate ordering forms a common Euler path for n-net and p-net

79 Optimized Stick-Diagram Layout Poly column separation Dd - only need to allow for one metal-to-diffusion contact Advantages: - smaller area and parasitic cap.

80 Exclusive-OR Gate Total no. of transistors: 12 (including two inverters for A and B)

81 And-Or-Inverter (AOI) Gate Enables sum-of-product (SOP) realization Pull-down net consists of parallel branches of series-connected nmos driver transistors

82 Or-And-Inverter (OAI) Gate Enables product-of-sum (POS) realization Pull-down net consists of series branches of parallelconnected nmos driver transistors

83 Pseudo-nMOS Gates Always conducting pmos for pull-up To reduce silicon area Nonzero static power dissipation V OL is not zero voltage any more Noise margin is smaller Depending on the ratio of pmos Load s k p to the pull-down net s equivalent k down,eq Application: In design where density is the no.1 concern (e.g., Memory)

84 CMOS Full-Adder Circuit sum _ out = A B C = ABC + ABC + ABC + carry _ out = AB + AC + ACB BC

85 Full Adder Schematic

86 Layout Using Minimum-sized Transistors co SUM A B C

87 Optimized Layout

88 Simulated IO Waveforms Carry-in B A Carry-out Sum

89 N-bit Binary Adder Ripple-Carry Adder Constructed by cascaded-connection of full adders Speed is limited by the long carry chain ( C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 ) S 0 S 1 S 2 S 7 FA FA FA FA A 0 B 0 A 1 B 1 A 2 B 2 A 7 B 7

90 Transmission Gate (TG) TG is a bi-directional switch between A and B which is controlled by signal C nmos passes perfect 0, but only up to (V DD -V T,n ) pmos passes perfect 1, but only down to V T,p

91 Operating Regions for TG Transmit logic 1 0 V V in =V DD I D I SD,p s d d s I DS,n V DD I sd,p getting smaller V out

92 Equivalent Resistance of CMOS TG Equivalent resistance is quite a constant

93 TG-Based Logic (Steering Logic) TG-based logic may be smaller than their standard CMOS counterparts

94 TG-Based Logic Arbitrary Function A B F 0 0 C 0 1 C 1 0 C n-well

95 Sample Layout F = AB + A C + A B C F x

96 Complementary Pass-Transistor Logic (CPL) Only n-network is used to steer input to output Might be faster than full TG-based logic But overall noise immunity is weaker because nmos cannot pass a full logic 1 CPL NAND2 CPL NOR2

97 Common Standard Cell Library Combinational Cells: Inverter Buffer 2-t0-1, 4-to-1, 8-to-1 Multiplexor NOR gates NAND gates And-Or-Inverter (AOI) gates Or-And-Inverter (OAI) gates Half Adder and Full Adder Cell Flip-Flops JK Flip-Flops D Flip-Flops with Set, Reset, Enable, Scan,, etc.

98 THE END of Combinational Logic Circuits!

99 Lecture 7 Sequential MOS Logic Circuits

100 A B C clk Synchronous Design Model A B C Combinational Logic OUT1 OUT2 FFs Sequential Circuits Comb. logic Comb. logic FFs FFs out1 out2

101 V i1 Cross-Coupled Inverters Bistable Element Circuit Diagram V o1 V o2 V i2 Voltage-Transfer Curves

102 SR Latch Circuit Gate-level Schematic Transistor schematic Truth Table

103 Capacitances of CMOS SR Latch

104 Rise/Fall Times of CMOS SR Latch

105 NAND-Based SR Latch Circuit Gate-level Schematic Transistor schematic Truth Table

106 Clocked Latch Circuit Gate-level Schematic AOI-based implementation Example Waveforms short glitch

107 All NAND implementation Clocked JK Latch S R

108 Truth Table of Clocked JK Latch

109 AOI Realization of JK Latch AOI-implementation NOR-Based JK Latch

110 Master-Slave Flip-Flop Q s Q s

111 Sample I/O Waveforms

112 CMOS D-Latch (I)

113 CMOS D-latch (II) Master-Slave D Flip-Flop Tri-state inverter A

114 Sample Layout of CMOS DFF Cross-coupled inverter-pair A Q m Q m

115 Setup & Hold Time A B C Comb. logic D Q FFs clk Setup time is due to D-to-Q delay: violated by long-paths Hold time is due to Clock-to-Q delay: violated by short-paths Valid data Comb. logic FFs out1 out2

116 Common Latch Types in Cell Library Transparent Latch JK Flip-Flop (Edge-Triggered) D Flip-Flop (Edge-Triggered) D SI SC MUX Primitive D Flop-Flop clk With Asynchronous Set and Reset With Extra Asynchronous Enable Signal Scan Flip-Flop Mux-Scan Flip-Flops SI means scan input SC means scan Control D-FF Q

117 THE END of Sequential Logic Circuits!

118 Lecture 8 CAD for VLSI Design ( Source ref. EECS244, Prof.K. Keutzer, U.C. Berkeley )

119

120 Performance analysis Circuit synthesis

121 Predicting Technology Trend - Moore s Law Logic capacity doubles per IC every 18 months ( 1975 )

122 Semiconductor Technology Roadmap Source Semiconductor Industry Association, ( SIA ), USA, Dec Deep Submicron Technology feature size < 0.25 μm.

123

124

125 Time-to-Market (Money)

126 Cadence, ViewLogic Cadence, Mentor

127

128

129 Level of Synthesis Techniques Speed of Designer Behavioural Synthesis Sequential Synthesis Combinational Synthesis

130 Module mux(q, a, b, sel) ; output q ; input a, b, sel ; reg q ; a or b or sel ) begin if ( sel ) q = a ; else if (! sel ) q = b ; else q = 1 bx ; end endmodule module statement Input/output port statement register statement behaviour statement

131 ( Register Transfer Level )

132 Module mux(q,a,b,sel) ; output q ; input a, b, sel ; reg q ; a or b or sel ) begin if ( sel ) q = a ; else if (! sel ) q = b ; else q = 1 bx ; end endmodule a b 1 0 sel q

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134

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136

137

138 Simulation Model Simulation Pattern ( HDL) ( vectors) ( your design ) ( stimulus ) ( waveforms )

139 Software simulation ( cont. ) Advantages of gate-level simulation 1. Verifies timing and functionality simultaneously. 2. Approach well understood by designers. Disadvantages of gate-level simulation 1. Incomplete results only as good as your vector set ; easy to ignore incorrect timing / behaviour.

140 LVS : Layout versus Schematic ( verification )

141

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