Lecture 9: Sequential Logic Circuits. Reading: CH 7
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1 Lecture 9: Sequential Logic Circuits Reading: CH 7
2 Sequential Logic FSM (Finite-state machine) Inputs Current State COMBINATIONAL LOGIC Registers Outputs = f(current, inputs) Next state 2 storage mechanisms positive feedback charge-based
3 Naming Conventions In our text: Ø a latch is level sensitive Ø a register is edge-triggered FF There are many different naming conventions Ø For instance, many books call edge-triggered elements flip-flops Ø This leads to confusion however
4 Latch versus Register q Latch stores data when clock is high (positive) q Register stores data when clock rises (positive) Clk Clk Clk Clk
5 Latches Transparent high Transparent low
6 Latch-Based esign N latch is transparent when φ = 0 φ P latch is transparent when φ = 1 N Latch Logic P Latch Logic
7 Timing efinitions (Register == FF) tsu T thold t Register ATA STABLE t T t + t + t c q plogic su tc q t + t t cdregister cd logic hold ATA STABLE t t cd : contamination delay = minimum delay - t su (setup time): the time that the date input () must be valid before the clock transition - t hold (hold time): the time that data input must remain valid after the clock edge - t c-q (clock2 delay): the worst case propagation delay
8 Maximum Clock Frequency t setup FF s φ t clk- LOGIC t p,comb t clk- + t p,comb + t setup T Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay
9 Mux-Based Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) = Clk + Clk In = Clk + Clk In
10 Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Small!! Converting into a MUX Forcing the state (can implement as NMOS-only)
11 Mux-Based Latch - Reduction of the clock load - But, V th drop low noise margin - Increase power consumption M M NMOS only Non-overlapping clocks
12 Master-Slave (Edge-Triggered) Register negative positive Two opposite latches trigger on edge Also called master-slave latch pair à FF (Flip-Flop)
13 Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 I 1 T 1 M I 4 T 3
14 Clk- elay t ( ) c q L H t ( ) c q H L T (ns)
15 Setup Time I 2 -T 2 I 2 -T 2 fail (a) T setup = 0.21ns (b) T setup = 0.20ns
16 Reduced Clock Load Master-Slave Register Reduce the clock load at the cost of robustness and complexity remove Feedback trans. gate T 1 I 1 T 2 I 3 I 2 I 4 I 2 should be weaker than T 1 I 4 can affect the stored data when T 2 is on (reverse conduction)
17 Avoiding Clock Overlap X A B Race between and B (a) Schematic diagram Clock skew! (b) Overlapping clock pairs
18 Storage Mechanisms Static (feedback) ynamic (charge-based)
19 Characterizing Timing t c2q and t d2q are easy to measure, But how about t setup and t hold t 2 2 Clk Clk t C 2 C2 Register t C 2 C2 Latch
20 More Precise Setup Time 1.05t C tc 5% increase in delay + margin t C
21 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN master TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time
22 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time
23 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time
24 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP ata Clock T Setup-1 Time T Setup-1 t=0 Time
25 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay T Clk- Inv1 CP ata Clock T Setup-1 Time T Setup-1 t=0 Time
26 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time
27 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time
28 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- T Hold-1 Time Clock ata T Hold-1 t=0 Time
29 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP 0 Clock T Hold-1 ata T Hold-1 Time t=0 Time
30 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M T Clk- Clk- elay Inv1 CP 0 Clock T Hold-1 ata T Hold-1 Time t=0 Time
31 ynamic edge-triggered register Simple and efficient (8 trs.) Ø NMOS only pass transistors possible 6trs. Ø Good for high-performance & low power Setup time == delay of transmission gate Hold time ~ zero (perfect clock) t c2q = 2 inverter delays + 1 transmission gate (T 2 ) Require periodic refresh (dynamic): registers are periodically clocked BUT, clock overlap is an important concern
32 Other Latches/Registers: C 2 MOS (Clocked CMOS) Insensitive to clock overlap (skew tolerance) V M 2 V M 6 Positive-edge triggered register 0 M 4 X M M 3 C L1 0 M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added to make circuit pseudo-static
33 Other Latches/Registers: C 2 MOS (Clocked CMOS) Insensitive to clock overlap (skew tolerance) V M 2 V M 6 Positive-edge triggered register 1 M 4 X M M 3 C L1 1 M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added to make circuit pseudo-static
34 Other Latches/Registers: C 2 MOS (Clocked CMOS) Insensitive to clock overlap (skew tolerance) V V V V M M 4 X M 6 M 8 M 2 X M 6 C L 1 C L 2 M 3 C L M 7 C L 2 M 1 M 5 M 1 M 5 Master Stage Slave Stage Master Stage Slave Stage 0-0 overlap 1-1 overlap Clock skew!
35 Other Latches/Registers: TSPC (True Single- Phase Latches) V V ynamic node V V Out In In Out Positive latch (transparent when = 1) Negative latch (transparent when = 0)
36 Including Logic in TSPC V V V V PUN In 1 In 2 In PN In 1 NAN In 2 Example: logic inside the latch AN latch Setup time increases but overall performance increases
37 TSPC Register ynamic inverter No!!! V V V M 3 M 6 M 9 Y M 2 X M M 8 X: 1 inv. delay X : 3 inv. delay M 1 M 4 M 7 negative latch positive latch clk
38 Alternative Approach: Pulse-Triggered Latches Ways to design an edge-triggered sequential cell: Master-Slave Latches ata Pulse-Triggered Latch L1 L2 L ata Clk Clk Clk Clk Clk Race avoided Opening time (=transparent period) is very short
39 Pulsed Registers V V M 3 M 6 V The length of pulse is controlled by the delay of the AN gate and the two inverters G M 2 G M 5 M P X G M 1 M 4 M N (a) register (b) glitch generation G (c) glitch clock Reduced clock load and the small # of transistors
40 Pulsed Registers Hybrid Latch Flip-flop (HLFF), AM K-6 and K-7 : can arrive after the clock goes high time borrowing?
41 Pipelining Project a REG a REG log REG Out REG REG log REG Out b REG b REG Reference Pipelined
42 Summary Sequential logic: output depends on input and current state Ø Latch Ø Registers (FF) Sequential elements eat up a significant amount of total timing budget + power resources Ø Extremely important to design carefully Ø Robustness is also critical - delay is best overall performance measure for edgetriggered registers since it combines both setup and - delays New designs like pulsed registers provide enhanced performance with added design complexity
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